Looking for help answering a few question about choosing parameters for a small voltage doubler circuit.
I'm looking to prototype a USB powered random number generator based on the shot noise of a Zener diode just entering its breakdown region. I understand the best noise is from Zener's with a breakdown above 5 volts, so I think I need a voltage doubler. I'm hoping to drive the voltage doubler with the signal from a GPIO port on the PSOC 5LP, and measure the output using a second pin. I found a nice old article from 1998 a similar approach, but I think it can be done with far fewer components today.
The article said: "Optimum noise performance is obtained from a 1N753A Zener diode, which has a 6.2-V Zener 'knee.'" It also mentioned that the optimal current for noise output was about 20 uA, generating about 20 mV p-p noise.
Based on this idea I've sketched out this circuit
So my questions are:
Does driving this from a GPIO port make sense?
Any reason I should try to make the drive approximate a sine wave, or can I just hit it with square wave like digital output?
Is there any limit to the frequency I should drive it at? I understand that higher frequencies will reduce the size capacitors I need.
With a frequency chosen, how do I size the capacitors.
P.S: Note that part of the design goal here is to have the SoC chip adjust the "doubled" voltage to optimize the noise generated. It won't need to fully double VCC.
Best Answer
Mark got everything right except to note that the anode of D3 has to be connected to +5V. Then when the PWM is low,C4 gets charged. When the PWM is high, that charge appears in series with the PWM output, hopefully about double.
Another approach to consider would be the venerable old 7660 or one of it's successors; it doesn't add much (if anything) to the complexity, and you have all kinds of design information oh the data sheet(s).