Electrical – Why two inverters in parallel

It is possible to construct a RAM out of flip flops and multiplexers. Such designs require a lot of silicon, but they can be very fast. Further, such designs inherently allow a RAM to any number of read ports independent from its write port and allow predictable behavior if a memory location is written and read on the same cycle (the read is guaranteed to yield old data for the duration of the cycle).

One could also construct a RAM using using a pair of inverters with pass gates on the feedback path, so that while new data was being written the circuitry performing the right would not have to fight the RAM's feedback transistors. Doing such a design "properly" in CMOS would require eight transistors for each RAM cell--a considerable improvement over using a flip flop per cell. Unfortunately, it would also require having both active-high and active-low select lines for each row.

A common approach to constructing large static RAMs is to have a pair of inverters which unconditionally feed back to each other, but have the P-channel side be "weak" enough to be overpowered by a couple of N-channel transistors (one of which may be quite big) in series with the column bus wire. This will require two column wires--each tied to one inverter through an N-channel pass transistor--but both pass transistors may be driven by a common row wire. A memory cell is written by enabling it and grounding one of the column wires. The transistor driving that wire will initially have to fight the cell's P-channel transistor, but once it has been overpowered the other side's P-channel transistor will turn on and the P-channel transistor one was fighting will switch off. The "bus contention" state will thus only exist for a moment.

Of course, once one gets into larger memories it becomes common to ditch the static-RAM architecture in favor of dynamic RAM which not only reduces each memory cell to a single transistor, but does so with a layout that ends up being more compact than almost any other layout one could do with the same number of transistors.

Assuming that the inverters are CMOS ones, the circuit is equivalent to:

^{simulate this circuit – Schematic created using CircuitLab}

While in the schematics you provided it seems like the circuits are interrelated, in fact they are not. Two completely separate blocks having a common input.

The basic idea behind this circuit is this:

• When M2 is ON (input voltage is LOW), the current can flow through the red LED
• When M3 is ON (input voltage is HIGH), the current can flow through the green LED

M2 and M3 are functioning as pass-transistors in this case.

The function of M2 and M4 are less important - they pull the voltages down/up when the LEDs are not required to be ON. I believe that the circuit would function without them as well. However, the presence of the full inverter allows for a very steep ON/OFF characteristic for LEDs - there is no wide transition region between ON/OFF states.