I am trying to debug my system with Xilinx Integrated logic analyzer and there is only a limited number of samples (131,072) that can be captured after the trigger signal, whereas I need about 350,000 to reach to the place of interest. Is there a way set up the ILA to start recording 300,000 clock cycles after the trigger signal?
Initial problem: I am trying to debug what happens on the beginning of the second frame of the video processing hls IP. Thus, my trigger signal is TUSER (start of the frame), and since I need the second frame, I need the ILA to trigger only when the TUSER goes HI the second time (skip the first low-hi transition). Is it possible to configure the ILA this way?