Electrical – Xilinx ILA to start recording after triger + Xnum clock cycles

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I am trying to debug my system with Xilinx Integrated logic analyzer and there is only a limited number of samples (131,072) that can be captured after the trigger signal, whereas I need about 350,000 to reach to the place of interest. Is there a way set up the ILA to start recording 300,000 clock cycles after the trigger signal?

Initial problem: I am trying to debug what happens on the beginning of the second frame of the video processing hls IP. Thus, my trigger signal is TUSER (start of the frame), and since I need the second frame, I need the ILA to trigger only when the TUSER goes HI the second time (skip the first low-hi transition). Is it possible to configure the ILA this way?

Best Answer

Not sure if there is a way to do this with the ILA directly. My guess is probably not to keep the complexity of the ILA logic down. What I would recommend is writing a little bit of additional logic to generate a new trigger signal based off of this specific condition that you're looking for, and then use that signal to trigger the ILA. Should only take a few extra lines of HDL to generate the trigger signal you need; either a one-shot timer setup to generate a delayed trigger or something to swallow the first (or perhaps every other) tuser pulse. Probably the simplest circuit would be to simply toggle a level on every tuser pulse, then you can pick which one you want by changing the trigger slope (rising or falling).