Electrical – Xilinx ILA to start recording after triger + Xnum clock cycles

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I am trying to debug my system with Xilinx Integrated logic analyzer and there is only a limited number of samples (131,072) that can be captured after the trigger signal, whereas I need about 350,000 to reach to the place of interest. Is there a way set up the ILA to start recording 300,000 clock cycles after the trigger signal?

Initial problem: I am trying to debug what happens on the beginning of the second frame of the video processing hls IP. Thus, my trigger signal is TUSER (start of the frame), and since I need the second frame, I need the ILA to trigger only when the TUSER goes HI the second time (skip the first low-hi transition). Is it possible to configure the ILA this way?

Best Answer

Not sure if there is a way to do this with the ILA directly. My guess is probably not to keep the complexity of the ILA logic down. What I would recommend is writing a little bit of additional logic to generate a new trigger signal based off of this specific condition that you're looking for, and then use that signal to trigger the ILA. Should only take a few extra lines of HDL to generate the trigger signal you need; either a one-shot timer setup to generate a delayed trigger or something to swallow the first (or perhaps every other) tuser pulse. Probably the simplest circuit would be to simply toggle a level on every tuser pulse, then you can pick which one you want by changing the trigger slope (rising or falling).

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The clock comes from a clock oscillator on the board. I am quite familiar with the Atlys board, we use a few of them for some networking research. It has a 100 MHz clock oscillator on it connected to the FPGA. All you need to do is add a pin to the top-level file of your design and assign it to the corresponding pin in the ucf file. You'll also need to specify the clock speed in the UCF file. The UCF file that we use for the Atlys board has the following information for the clock pin:

NET "clk" LOC = "L15" | IOSTANDARD=LVCMOS33; # IO_L42P_GCLK7_M1UDM (GCLK)
NET "clk" TNM_NET = "sys_clk_pin";
TIMESPEC "TS_sys_clk_pin" = PERIOD "sys_clk_pin" 100000 kHz;

This locates it to pin L15, where the oscillator is connected to the FPGA on the board. It then tells the toolchain the clock frequency of 100 MHz with a timing constraint.

The pin also needs to be sent through an IBUFG and BUFG before you can use it, like so:

module fpga_top (input wire clk, some_other_signals....)
    wire clk_ibufg;
    wire clk_int;
    IBUFG clk_ibufg_inst (.I(clk), .O(clk_ibufg));
    BUFG clk_bufg_inst (.I(clk_ibufg), .O(clk_int));

    your logic goes here...

endmodule

Then just use clk_int to clock your logic. The IBUFG and BUFG elements are required to get the clock signal into the global clock network so that it can effectively drive your design.

If you want to use a frequency other than 100 MHz, then you can create a DCM module with coregen and instantiate that instead of the IBUFG and BUFG elements (the DCM wrapper file will contain the necessary buffers). DCM modules will instantiate PLL modules on the FPGA to synthesize a clock frequency that is a rational fraction of the input clock (2, 1/2, 2/3, 3/4, etc.).

Here is a barebones example design for the Atlys board that uses a DCM to generate a 125 MHz clock: https://github.com/alexforencich/verilog-uart/tree/master/example/ATLYS/fpga .

Best Answer

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