Electronic – 12V to 5V buck converter 3A PCB

layoutpcb

I am creating my first 12V to 5V buck converter with the TI TPS56339. I've heard that the PCB layout is critical and before I send the PCB to production I wanted to get it reviewd. I tried my best to follow the guidelines for the component layout.
Could you please review my layout?

Schematic
PCB Layout

Thanks

Thanks for your answers. Based on your feedback I created another design. Unfortunately it is not possible to change the thermals on individual pads in Eagle. Is the design better now?

PCB2

Here is my 3rd design. I switched to the LMR23630 due to better part availability. I tried to follow the design guidelines in the data sheet. The output capacitor is a little far away from the IC's PGND pin. Will that be a problem?

3rd PCB Design

Best Answer

Before you commit to a design, you need to have Design and Test Validation Specs (for DFT) These include parameters like; Environmental stress, efficiency, output voltage regulation, load transients, loop response, output ripple, input ripple, and start-up surge current, rise time and overshoot. EMI V/m near & far field.

What are your specs?

I think you made too many deviations from the recommended design. (Eval design not FCC-Approved)

from TI datasheet
1. VIN and GND traces should be as wide as possible to reduce trace impedance. 
      The wide areas are also of advantage from the view point of heat dissipation.
2. The input capacitor and output capacitor should be placed 
      as close to the device as possible to minimize trace impedance.
3. Provide sufficient vias for the input capacitor and output capacitor.
4. Keep the SW trace as physically short and wide as practical to minimize radiated emissions.
5. Do not allow switching current to flow under the device.
6. A separate VOUT path should be connected to the upper feedback resistor.
7. Make a Kelvin connection to the GND pin for the feedback path.
8. Voltage feedback loop should be placed away from the high-voltage 
      switching trace, and preferably has ground shield.
9. The trace of the VFB node should be as small as possible to avoid noise coupling.
10. The GND trace between the output capacitor and the GND pin
      should be as wide as possible to minimize its trace impedance.  (nH/mm)
  • Copper heatsink area insufficient.
  • lack of microvias around side of L which is an unshielded inductor pat of a large dI/dt and dV/dt, current loop of unintended radiation. (EMI)
  • Critical feedback traces too long.
  • Smaller inductors tend to have higher DCR
  • lack of DFT test points for a diff probe

I am just "scratching at the surface" of the design differences enter image description here

enter image description here

For more details on DC-DC PCB layout, read Rohm's paper.

Major problems that arise from inappropriate layout may cause increase in noise superposed by output and switching signal, the deterioration of regulator, and also lack of stability. Adopting an appropriate layout will suppress these problems to occur.

Keep wiring of return path away from noise causing areas, such as inductor and diode. enter image description here

Switched current loops look big in above "analogic" diagram but must be small in the physical layout. (loop antenna)

enter image description here

LC-diode placement matters to minimize loop area shown in the schematic.

enter image description here

Copper Weight matters for heat rise. enter image description here

Bottom Line : Without Specs (read introduction again), How will you verify that it works?

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