If I understand correctly, you are looking for an analog multiplexer with the option of setting the channels to high impedance.
If so, the 4052 or 4053 should do the job, they have an enable input which sets the ports to high impedance.
As mentioned in the comments, it might be a good idea to post a rough schematic of what you are doing, as it's a little unclear at present.
The question seems rather confused in several respects...
1) It is unclear whether you want to implement 3-state logic or an open-drain interconnection.
In the former, the driving device DOES use a push-pull output, driving 0 or 1 onto the bus. The other devices, meanwhile, must abstain from driving until some separate system signals that it is their turn.
In the latter, the bus is always pulled to '1' by a resistor, and any device may pull it to '0'. In this case, there is no harm done if several devices drive the bus simultaneously, though any messages may be corrupted.
2) You say you want a "floating" bus to indicate that the bus is free. In neither case is this normally possible (there is no logic primitive that can detect that a bus is floating). This is why in tri-state logic there must be another system (bus arbitration logic) to keep track of who has the bus, and give each device a turn.
Now as to the specific question of transmission gates : either of these systems can be trivially implemented using transmission gates, though there are other and sometimes better ways.
Tri-state logic can be implemented using a normal push-pull (totem-pole) output, and a transmission gate between the push-pull output and the bus. The bus arbiter simply switches the transmission gate on or off.
It is often more economical to turn off both transistors in the push-pull output instead.
Open drain logic can be implemented with a transmission gate by simply connecting one side of it to ground, and the other to the bus. Now simply turn it on to pull the bus low.
Best Answer
A typical output stage uses a totem-pole or push-pull configuration. For a logic 0 the lower transistor is on for a logic 1 the upper one.
Now it is possible to turn off both transistors which neither drives the output high or low. The circuit is basically disconnected (high impedance, high-Z).
A circuit that accomplishes that is shown below.
When enabled the signal QP12 and QN12 are on the inverter formed by QP11 and QN11 can drive the output.
In the disabled state QP12 and QN12 disconnect the inverter from the supply and the output is in a high impedance state regardless of the input signal.