I'm about to start placing components on my very first 4-Layer PCB (wrapping up schematic and MCU software tested on 2-layer pre-prototype, all runs surprisingly ok, but still 2 layer meh). I've studied a lot of materials, videos from Robert Feranec and Rick Hartley on grounding. While a lot of stuff there is really complicated or assumed understandable, it's pretty damn hard, nevertheless I've learned a lot (even if understood not 100%, but most of it), but I still have a few questions I want to clarify. Several hours of googling brought nothing, and there is nobody I can ask a specific question (or a few).
My design is up to 20MHz MCU system, UART, SPI, I2C, has DAC and ADC, max system current 5V 1A.
Planned stackup: Sig-GND-Vcc(5V)-Sig.
Question 1: GND pours on Sig planes. Yes or no? Most examples actually don't have pours, but explicit answer would be welcome (and short why).
Question 2: the decoupling capacitor should have a via to the POWER layer (3) and the GND layer (2). BUT: I can't have connections to both Vcc and GND planes from Top and Bottom layer: EAGLE was refusing to allow me make vias like that (1 to 4 ok, 1 to 2 ok, 3 to 4 ok, but only EITHER 1 to 3 or 2 to 4, DRC tells me NEIN when I try both; Eagle numerates layers as "1", "2", "15" and "16" respectively). I googled out it was for manufacturing reasons, which made sense now that I think about it. So how do I place decoupling caps for the chips on the bottom? Bottom (layer 4) can't have direct via to GND (2). What do I do about it?
Question 3: I saw a lot of material on impedance and all, but layer switching was only mentioned briefly and kinda "assumed easy and clear" that I need to switch reference plane or something (since I was against GND plane on layer 1, but against Vcc on layer 4). Well, I have actually no clue what any of that means. Say, I have an I2C signal on layer 1. Suppose, I really need to switch it to layer 4. Signal's via goes straight to 4, no problem. What do I do with current return path, which was on GND plane right under I2C trace(right)? And again, Bottom layer can't even have direct via to GND.
Question 4: mechanical one. Internal layers in JLCPCB guidelines that I looked at as an example, are by default twice thinner than outer layers. So GND and 5V planes are thin. Should I care? (5V 1A max for system)
Unfortunately, the whole thing is very confusing at the moment. 2 Layer board required less brainwork. Pour more, think less. Now I understand why it's bad (I guess, "worse" is the correct word), but I'm stuck between rejecting 2 layer design wishing to make things better and being unable to adopt 4 layer design even if I spend a lot of time researching it. I grasped the key ideas and concepts, but some smaller practical details are omitted wherever I looked.
I would appreciate if you could also share some materials like "4 layer PCB for dummies" or something in addition to specific replies to my questions. Can't have too much information.
Also, maybe someone could give a link to a good simple 4-layer PCB design I could look at in Eagle or Altium (have trial version of that, wish I could work in it always). No DDR stuff, more of my caliber – MCU and peripherals, if possible. Thank you.
Best Answer
I agree with some comments in the answers above, but not completely so I'll offer another perspective:
As was mentioned above, Hartley is talking about passing EMI compliance with fast data rate applications. You'll have fast enough rising/falling times to generate a lot of noise but unless you care about passing EMI, or are running analog nearby, you probably don't care.
I do high speed work into the 100's of Gbps per lane professionally as well as millimeter wave design to nearly 100GHz, so I live in the middle of these problems every day. But when I'm messing with a micro at 20MHz for hobby fun, I don't much pay attention to any of this except when I'm mixing in analog signals and even then, if the digital lines will be quiet during a data conversion, I still don't worry about it.
The Signal1-GND-Vcc-Signal2 is something an EMI or high speed signal integrity guy would push back on. The energy in the Vcc plane will be in the dielectric between Vcc and GND. Signal2 will have its energy in the two dielectric layers between Signal2 and GND. These two energy fields (Vcc and Signal2) will intermingle and cause interference between each other. It probably doesn't matter to you so go for it, but be aware that this issue is out there.
Signal-GND-(core)-GND-Signal is an ideal stackup. GND-Signal-(core)-Signal-GND is great, too. To "properly" add a power plane it would be nice to go to a 6 layer board- Signal-GND-Power-(core)-Power-GND-Signal or something like that. But again, you probably don't care, and properly routing signals gets complicated so don't sweat it.
Q1 - Ground pours on signal layers? Generally no. You're as likely to cause interference as to mitigate it until you develop a good understanding of how EMI works. Lots of examples of this out there, and hard to mitigate noise using lateral grounding on a PCB, it just doesn't work well.
Q2 - For vias, you can use vias that are drilled through all layers and plated for the full length of the PCB but are only connected to the metal on layers you actually need electrical connection to. Eagle supports this, keep beating at it and you'll figure out how. So, put a cap on top and put vias next to it that connect from top layer to power and gnd but no other layers.
Q3 - You can run signals from layer 1 to layer 4. The ground reference will flip from the top of the GND metal foil to the bottom of GND metal foil. No problem.
Q4 - It's standard to have 0.7mil (1/2 oz) copper on inner layers and 1.4mil (1 oz) on outer layers. You don't care.