Electronic – 555 Timer in Bistable Mode – Unexpected Behavior When Removing Power

You can't use the main timing resistor and capacitor to generate your trigger signal. As you discovered, this is exactly equivalent to the astable configuration.

Instead, you need to provide a separate resistor (to Vcc) and capacitor (to ground) for the Trigger pin. The time constant for this pair should be short relative to the main timing period, but long relative to the risetime of the power supply.

These components will hold the trigger low while the chip powers up, but then allow it to go high a short time later. Once the timer has timed out, the main timing capacitor will be discharged, but the trigger capacitor will not.

Among experienced EEs it is a well known fact that electrolytic capacitors (like that 100 uF one) can have huge tolerances. These capacitors often have a 20 to 30 % higher value than their nominal value. As there caps are mostly used for supply decoupling that is usually irrelevant.

You are trying to make a (somewhat) precise timer with a timing of a few seconds. You cannot expect much precision from this circuit, the NE555 is not very well suited for longer timings. Most EEs would use a faster running clock and a counter, the CD4060 (14-stage ripple carry binary counter) is a candidate for that. You can make it monostable if you play with the reset.

To solve both circuit problems I would add a small (10 nF) capacitor in parallel with R2, this will force the Trigger to be slightly longer when the button is pushed. You could try a different combination of R1, C1 like 1 Mohm and 5.6 uF. That way the capacitor is smaller making it easier for the discharge transistor in the NE555 to discharge it.