Electronic – a flip flop

circuit analysisdigital-logicflipfloplatchmemory

There seem to be a number of different definitions of flip-flops and latches out there, some of which are contradictory.

The Computer Science text book for the course I teach is probably the most confusing (in fact I have little faith in the book because it’s just plain wrong in several places).

I am comfortable with the workings of latches (SR, gated SR, gated D), and the difference between level triggered and edge triggered devices, at least in terms of logic gates and timing diagrams. However, I am still looking for a concise definition of a flip flop and of a latch.

This is what I believe so far:

“A flip flop is an edge triggered bi-stable device that can store 1 bit”.

“A latch is a level triggered bi-stable device that can store 1 bit.”

I’ve had a look at previous posts on this website about this and, as enlightening as they are, I am still looking for something definitive.

My current understanding, which I want to check, is in the diagrams below…

Side by side are what I understand are two implementations of a level triggered gated D latch.

Below these is a positive edge detector, at that brief moment when the NOT gate has not yet responded to the change input from low to high, namely the rising edge (red is 1 blue is 0).

In the last diagram, the edge detector has been fitted to a dated D latch and this is what makes it a flip-flop.

enter image description here

Is the last diagram really a flip flop, or is it still just a latch?

And why do we need the master slave version given, that this device is so much simpler?

Best Answer

I have been thinking about this definition a lot today.

As others pointed out, the exact meanings will vary. On top of that, you will probably see more people get this wrong, even on this site, than right. I don't care what wikipedia says!

But in general:

  • A flip flop will change it's output state at most once per clock cycle.
  • A latch will change its state as many times as the data transitions during its transparency window.

Additionally,

  • A flip flop is very safe. Almost fool-proof. For this reason synthesis tools usually use flip flops. But, they are slower than a latch (and use more power).
  • Latches are harder to use properly. But, they are faster than flip flops (and smaller). So, custom circuit designers will often "spread the flip flop" across their digital block (a latch on either end with opposite phase) to squeeze some extra picoseconds out of a bad timing arc. This is shown at the bottom of the post.

A flip flop is most typically characterized by a master-slave topology. This is two coupled (there can be logic between), opposite phase latches back to back (sometimes in industry called L1/L2).

This means a flip flop inherently consists of two memory elements: one to hold during the low cycle and one to hold during the high cycle.

A latch is just a single memory element (SR latch, D latch, JK latch). Just because you introduce a clock to gate flow of data into the memory element does not make it a flip flop, in my opinion (although it can make it act like one: i.e. more rising edge triggered). It just makes it transparent for a specific amount of time.

Shown below is a true flip flop create from two SR latches (notice opposite phase clocks).

true d ff

And another true flip-flop (this is the most common style in VLSI) from two D-latches (transmission gate style). Again notice the opposite phase clocks:

true flip flop tg style

If you pulse the clock to a latch quickly enough, it starts to resemble a flip flop behavior (pulse latch). This is common in high speed datapath design because of the lesser delay from D->Out and Clk->Out, in addition to the better setup time granted (hold time also must increase, small price to pay) by transparency through the duration of the pulse. Does this make it a flip flop? Not really, but it sure looks acts like one!

However, this is much harder to guarantee to work. You must check across all process corners (fast nmos, slow pmos, high wire cap, low wire r; as an example of one) and all voltages (low voltage causes problems) that the pulse from your edge detector remains wide enough to actually open the latch and allow data in.

For your specific question, as to why it is considered a pulse latch instead of a flip flop, it is because you truly only have a single level sensitive bit storage element. Even though the pulse is narrow, it does not form a lock-and-dam system which creates a flip flop.

Here is an article describing a very similar pulse latch to your inquiry. A pertinent quote: "If the pulse clock waveform triggers a latch, the latch is synchronized with the clock similarly to edge-triggered flip-flop because the rising and falling edges of the pulse clock are almost identical in terms of timing."

EDIT For some clarity I included a graphic of latch based design. There is a L1 latch and L2 latch with logic in between. This is a technique which can reduce delays, since a latch has lesser delay than a flip flop. The flip flop is "spread apart" and logic put in the middle. Now, you save a couple gate delays (compared to a flip flop on either end)!

latch based design

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