Electronic – a “half latch” in an FPGA


In a paper about radiation hard FPGAs I came across this sentence:

"Another concern regarding Virtex devices is half latches. Half
latches are sometimes used within these devices for internal
constants, as this is more efficient than using logic".

I have never heard about an FPGA device primitive called a "half latch".
As far as I understand, it sounds like a hidden mechanism to "source" a constant '0' or '1' in the backend tools…
Can anyone explain what exactly a "half latch" is, especially in the context of FPGAs, and how they can be used to save logic?

EDIT: The paper were I found this was A Comparison of Radiation-Hard and Radiation-Tolerant FPGAs for Space Applications

Best Answer

A half-latch is a gate with positive feedback implemented with a weak pull-up transistor:


simulate this circuit – Schematic created using CircuitLab

When the input is actively driven, it overrides the signal coming from the weak pullup. When the input is in Z-state, the weak pullup can keep the logical "1" at the input (and "0" at the output) indefinitely. It will not keep the opposite state reliably, hence "half-latch".

Why would someone want a half-latch instead of a full latch? For some signals it doesn't make sense to be able to store both constants. For example, a D-flipflop can have enable input only latched high, and reset input only latched low, otherwise it will simply be eliminated during synthesis. That's the kind of signals for which half-latches are used: they are either latched to default value, or driven by interconnect.