Electronic – Altera Quartus – How to simulate a different Entity

Check Avalon-MM and Avalon-ST specifications here: http://www.altera.com/literature/manual/mnl_avalon_spec.pdf. You'll also find all the timing diagrams in this PDF file. Usually, the control interface is done using Avalon-MM interface, which has 32bit read and write data ports, plus 32bit address, plus control signals and IRQ if needed. Avalon-ST is used for streaming devices, so You can use it for Audio.

Xilinx UCF is a constraints file format. It is used to apply various constraints on the design to the Xilinx tools, including but not limited to pin locations, timing, and area. When mapping your RTL (VHDL) design to a physical device, you will minimally need clocks and pin constraints at the top level, but constraints for real designs can go much further than this. Xilinx has a User Constraints Guide on this subject.

You can use the system clock if it meets your needs. Very often, real designs require clocks at a specific (lower) frequency, or multiple clocks at different frequencies, which is where clock dividers would be used.

A gentle dead tree introduction to VHDL programming for Xilinx I can recommend is this book. I recommended a book, since I have not found online HDL tutorials nearly as concise or complete as those for software. You should also scour Xilinx's online documentation for their tools and the part(s) you're using.