You don't need that Sallen-Key filter before your amplifier if you are already filtering with the input RC high-pass filter.
You can simply AC couple the input, bias the amp and gain it up.
simulate this circuit – Schematic created using CircuitLab
Some key things to note from this circuit:
The input RC filter in your original circuit had a cutoff \$F_c\$ of 1 Hz but your text said 0.5Hz. 0.5Hz is actually better, so I kept that and changed the 0.1μF input capacitor to 0.22μF.
$$F_o(R1C1) = {{1}\over{2 \pi R1 C1}} = {{1}\over{2\pi(220nf)(1.6M)}} \approx 0.5Hz $$
Note that the RC combination of R2C2 with the opamp forms an active high-pass filter which should equal or be close to R1C1:
$$F_o(R2C2) = {{1}\over{2 \pi R2 C2}} = {{1}\over{2\pi(68μF)(5K)}} \approx 0.5Hz $$
Unfortunately, this means a fairly large C2 capacitor, because you need to balance that against R2 and the gain of the op-amp that you want (G=100).
You might be able to get around that by using two gain stages x10 of equal design. This way you can use larger R2 values and thus a smaller C2. For example, x10 would be R3=200k, R2=22k, C2=15μF, and you need two of them.
Also note that the LM324 cannot reach the top rail, so it will clip with such a high gain. You should use a better rail-to-rail output amp when working with 3.3V
EDIT: Oh, on further review, I think I see you want to follow the input high-pass filter @ \$F_c\$ = 0.5Hz with an active low-pass filter with \$F_c\$ = 5Hz, with the goal of making a bandpass filter out of the two.
If that's the case, then you will want to just AC couple the second stage again and bias it at Vbias. Furthermore, you'll want to change the Sallen-Key cutoff point to something higher than 5Hz if you want to pass 1-5Hz. Remember these are the 3dB down points, so you want some extra bandwidth. So if you want to pass 1-5Hz, then you should use a high pass at 0.5Hz or less and a low pass at 15Hz or more.
Change your 68K resistors on your Sallen-Key low pass filter to 22k and you will have a \$F_c\$ of 15Hz. This way you won't roll off and attenuate your 5Hz in-band signal too early.
simulate this circuit
The offset voltage of each of the op-amps you're using can be as much as +/-3mV at room temperature. So, the difference between two outputs could be as much as 6mV different from the inputs with unity gain. You're seeing 5.4mV which is large, but within specifications and therefore plausible.
Since you don't have much gain in the first stage (only 3) you also have to consider the offset voltage in the second stage. In any case, 638 times your measured differential input offset voltage of 5.4mV + 2.5mV signal is almost 5V.
You can either use better op-amps (such as autozero or 'zero drift' types) or null out the offset voltage by some means (trimpot or reduce the gain and do it digitally). You should also consider the drift of the op-amps you're using which is not guaranteed, but is fairly reasonable typically (+/-1.7uV/K).
Best Answer
This circuit/sensor uses 81pF as the resonant cap. Thus we can have substantial input capacity of the amplifier (several PF) without serious upset to the energy storage and tuning. To avoid dampening, the interface needs to have impedance >> the reactance of 1Henry at 17,000 Hertz, which is about 100,000 ohms.
First, lets bias that sensor to VDD/2 approximately.
Use two 1 MegOhm resistors in series, running from VDD to Ground. Place 100pF cap from the midpoint to your sensor. We now have VDD/2 voltage plus your sensor. The interface resistance is 1M || 1M or 500,000 ohms, which supports a Q=5 for your sensor. That is about what I observe (the rate of buildup of the voltage) in your simulation. You can use 3.3M or 10Meg ohms (two in series) if you wish.
Get yourself some opamp that uses FET (CMOS) technology. Read the datasheet, or examine the INPUT BIAS CURRENT for room temperature operation. The input bias current will be picoamps ( << 1 nanoAmp, may be the spec value) for a CMOS opamp. Such low input bias currents ensure the VDD/2 voltage divider will continue to define the DC input voltage.
Ensure the opamp works on 0/+5 volt rails. Because of how this circuit (to be detailed below) operates, you do not require rail_rail input nor rail_rail output, but such performance will not degrade the performance. Do not use micropower (1uA Iddq) opamps; the speed will be way too slow.
Connect the Vin+ of the opamp to that 1Megohm + 1Megohm midpoint.
From Vin- of the opamp to Ground, install a 1Kohm in series with 0.1uF cap. This series network is DC_blocking, with negligible effect at 17,000Hz. [ hmmmm the time constant of R * C = 1e+3 * 1e-7 = 1e-4 or 100uSec, which is 1,600 Hertz, so yes has negligible effect.]
From Vin- to Vout of the opamp, install the Feedback network --- use (initially) a 100,000 ohm resistor. Even if the opamp has only 1MHz UGBW, you should observe a gain of 1,000,000 / 17,000 = 55X stronger signal on the opamp output.
An opamp with UGBW higher, such as 3MHz or 10MHz, should provide 100X gain (40dB).
And the output will be biased at VDD/2, so first verify the output DC is (near) VDD/2, then switch the scope to AC coupling, and verify the expected gain.
I've suggested the 1Kohm and 100Kohm resistors be used to set the gain, because high values will allow phase_shifts in the opamp's feedback path, which may cause ringing or oscillation. You don't need that bother.