Electronic – Amplitude stabilisation of LC oscillators

Relaxation oscillators are prone to such behavior because

1. When they are very near the threshold, it only takes a very slight disturbance to push them over 'sooner' than they should go
2. When a relaxation oscillator hits its threshold, it's apt to generate a disturbance on the power supply.

Three ways of avoiding this problem are to use a resonant oscillator design, do a better job of isolating the oscillators and their power supplies, or use a slightly modified relaxation oscillator which subtracts a fixed amount of charge from its storage cap each time it trips, rather than discharging the cap to a fixed level, so that even if it trips "early" on one cycle, it will compensate by taking longer to trip on the next cycle. Note that the latter approach won't entirely avoid phase jitter when oscillators' phases pass near each other, but it will greatly reduce the "locking" effect.

Edit

I don't have a practical design handy, but consider the following main circuit with a constant current source, two caps (for discussion, assume they're equal), two NPN transistors with base resistors (for discussion, assume trivial base-emitter current is required to turn them on), and some control circuitry:

1. The cathodes of C1 and C2, and the emitter of Q2, are grounded.
2. The anode of C1 is connected to a positive constant-current source and the collector of Q1, and also feeds into the control circuitry.
3. The anode of C2 is connected to the emitter of Q1 and the collector of Q2. The emitter of Q2 is connected to ground.
4. The bases of Q1 and Q2 are connected via resistors to separate outputs from the control logic.

Behavior should be as follows:

1. Reset the circuit by turning on both Q1 and Q2, so both caps start out discharged.
2. During the first part of each cycle, Q1 should be off; Q2 may start out on, but should switch off sometime before the next step; C1 will charge through the constant current source, while C2 will sit at zero.
3. Once C1 reaches a certain threshold, which should be at least twice the voltage level output by the control logic, Q1 should switch on. This will transfer an amount of charge from C1 to C2 equal to the emitter voltage on Q1 (i.e. the voltage from the control circuitry, minus 0.7 volts), times the capacitance. If C1 and C2 are equal, this will drop the voltage on C1 an amount equal to that emitter voltage.
4. Sometime after C2 has reached its equilibrium voltage, but before C1 reaches the threshold again, Q1 should switch off and Q2 switch on.
5. Repeat the cycle, switching Q2 off sometime after C2 has been discharged.
6. If turning on Q1 for awhile doesn't push C1's voltage below the threshold, then the circuit should be reset (by turning on Q2 while Q1 is still on). Unless the transistors take too long to charge or discharge C2, or the control circuit forces overly-slow timings on them, this should never happen.

Note that in this circuit, it won't matter how long Q1 and Q2 are switched on each cycle provided they're switched on long enough for C2 to reach its equilibrium state. The only path for charge to flow into C1 is the constant current source, and the only way for current to flow out is by filling up C2. The only path for current to flow into C2 is from C1 (assume transistor BE current is trivial), so each time C2 is charged and discharged it will take a fixed amount of energy from C1. The net effect is that the overall average oscillation rate will be the number of amps into C1, divided by the number of coulombs dumped each cycle in C2, independent of the threshold voltage for C1 or the durations that Q1 and Q2 are switched on.

Try this circuit.

The upper-left op amp and one capacitor form a charge accumulator. The other cap and mosfets form a charge dumper which will dump a fixed amount of charge each time the mosfets are cycled with non-overlapping signal. The bottom center is a control circuit which will generate discharge cycles if there's too much charge on the cap. I have outputs showing the generated pulses, generated pulse/2, and generated pulse/16, along with 100Hz and divided-down reference waves for comparison.

Note that you may adjust the threshold voltage for the comparator; this will vary the phase of the output, and with the slider values I've provided may delay it by up to 16 cycles. Note, however, that when the slider is returned to the right (+2 volts) the wave will return to being essentially in phase with the original, and will count at up to 1/4 of the 673Hz (value chosen arbitrarily, but must be at least 4x count rate) signal until it has "caught" up.

The oscillation frequency is determined solely by the charge current, the anode voltage of that cap which is held by the left op amp, and the size of the dumping cap. You may find it interesting to play around with the size of the accumulating cap; it will affect phase, but not frequency. The simulated oscillator speed isn't quite precise, but it's pretty close. The notable thing is that one can move the threshold slider around to try to jinx the oscillator, but it will not only get back to being in the correct phase relationship with where it should have been but the count/16 output will show the correct phase as well.

Quartz crystal is not the same thing as crystal oscillator.

Quartz crystal consists of real physical crystal that has precise dimensions. The higher the desired frequency, the smaller the crystal must be. So it is practical to make them only in certain range (common values are 4 MHz - 40 MHz, and then low-frequency 32 kHz for RTCs).

It works by piezoelectric principle. Applied voltage causes it to contract and vice versa. At certain frequency, it gets into mechanical resonance which is projected into electrical resonance.

Quartz crystal oscillator is circuit that contains a quartz crystal and produces periodic signal. It can be integrated or constructed from individual components. One example is single-inverter oscillator.

The part numbers you provided are almost certainly form an 4MHz crystal.