I'm trying to understand this sentence (from this answer):
So if your application has high ripple current and you don't need the
ESR zero for stability then a low ESR cap will likely be the way to
go.
Electronic – an ESR zero in a power converter’s output filter ? (#ExplainLikeI’m5)
esr
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Best Answer
Without the equations (like you're 5), an ESR zero 'speeds up' the response, that is it reduces the phase shift, around the feedback loop, and so allows you to make an unstable loop stable.
Consider a sudden step of current into the output capacitor.
With a pure capacitance, no ESR, the output voltage will start to ramp, as the current gets integrated.
With a capacitor with some ESR, Equivalent Series Resistance, the current flowing in the resistance will give an immediate step change in voltage, which is then followed by a voltage ramp as the current gets integrated.
It's this immediate step in voltage that makes the loop behave 'better' for stability, although it's worse for output ripple (you win some, you lose some).
It's called a zero because when you do the maths properly (like you're 20), and form an expression for the gain of the regulator, the term containing the ESR is on the top of the gain equation, so when that term goes to zero, the whole gain does. Most other terms, the poles, are on the bottom of the gain equation, and when they go to zero, the gain becomes infinite and you get oscillation.
Why it matters has to do with accidents of history. The original single IC regulators (like 780x) use emitter follower output stages, which are fast and low impedance, but have a large dropout voltage. This was when the only large caps available were aluminium electrolytics, with a high ESR. Low impedance output and high ESR cap meant rock solid stability without much trying. Then people wanted LDOs, so a common collector PNP stage was used for output, which is a slower device with a higher output impedance. Tantalums became available, with a lower ESR than alli, but it was still non-zero. We could still get stability by specifying a minimum ESR and a particular capacitor range. Then big value ceramics appeared, smaller and cheaper than tants. These had (to all intents and purposes) zero ESR. LDOs used with them would sometimes oscillate, not always, but often enough. Stability was not always compromised, but was no longer ensured. The worst problem was when the prototype worked on the bench, and then a new batch in production failed, very expensive to fix. Manufacturers tweaked their designs, prohibited ceramics in the data sheets, but users kept getting it wrong and building oscillating regulators. This gave LDOs a bad name, and put an aura of magick around the output capacitors. Eventually, regulator manufacturers accepted the problem and designed a new regulator topology which assumes the worst case zero ESR output cap, and handles the stability properly inside the regulator. These are marketed as 'stable into ceramic' or 'AnyCap' regulators.