There are several points in the AD843 datasheet that appear to be relevant.
I first spotted the "Overdrive Recovery" time (under the general category of "Frequency Response"). Note that the recovery time for positive overdrive (found in your negative peak detector) is significantly longer than the recovery time for negative overdrive (found in your positive peak detector). Half a microsecond when your pulse width is on the order of 2.5 µs (half-cycle @ 200 kHz) could be significant.
Second, the datasheet specifically mentions that the AD843 has trouble driving capacitive loads. Your 10 nF capacitor is more than an order of magnitude larger than any example load they mention in the datasheet.
Third, there is a peak detector circuit given in the datasheet. The topology is slightly different from yours, but more significantly, they use the AD843 in the output stage, but use an AD847 in the input stage "since the AD847 can drive an arbitrarily large value of capacitance".
You've got there a low pass filter. Let's split the three cases:
1: It depends on the angle of rising voltage line. But in all cases the capacitor will keep rising it's voltage while the input is still rising. The variation rate of input voltage can be associated with a input frequency (roughly). So low rates will make capacitor voltage almost equal to input voltage and high rates will produce higher voltages accross the resistor (low and high frequency filtering). This happens because initially you will have some voltage accross the capacitor (let's say zero volts) and then when you put something into the input, you will create a voltage difference accross R1. This may produce a current (Ohms law) and this current will be the one which will fill the capacitor. As long as the capacitor is rising its voltage, the voltage accross R1 will reduce. So its current will also reduce. So capacitor rising rate will fall. You could make your input vary just like the capacitor rate is varying so you will also have a straight line rising in the output. The RC constant will tell you the capacitor "limitation" of rising its voltage.
2:With a sine wave you could analyze it like a LTI (linear time invariant) system since you got there a simple low pass filter. There is a bode plot of a low pass filter:
We can see that low frequencies will pass through the filter and as long as the frequency rises above fc (cut off frequency), it starts to fall. Bode plots uses logarithm scale and is generally an approximation, so we may think that under fc the filter does not act. It does make some difference but it is very low. You can think of the first example: some slopes make the capacitor "fill's" as fast as the input. But at a given slope at the input it will be faster than the capacitor rate (given by RC). The higher your input slope, greater will be voltage accross R1 since you got the same RC limitation of time. This is the filter principle. This time constant is direclty related to your fc (cut-off frequency).
In an intuitive way: you can imagine the sine variations as a sequence of different variations of the first case. So the higher the sine frequency will be like higher slopes of input voltage (and greater will be the 'difficulty' of the capacitor to rise as fast as the input).
3: The square wave is simple to understand when you imagine what happens when you turn on and off a +VDC supply (step response). Note that if your input is at zero and then you apply a +5VDC (for example), it will also be like the first case. But now you got ideally a slope of 90 degrees. Your input will vary at the highest speed to a given voltage which of course your capacitor won't be able to rise as fast as it. But now you've got a constant voltage at the input so you have a voltage accross R1. As the time goes on, this current through R1 will charge the capacitor so the voltage accross R1 will fall (since its input is constant at +5VDC now). But at a given point the square wave will fall. The same process will occur but now in the inverse way. This image shows what will happen:
Note that depending on your square wave fundamental frequency, you may not be able to rise the capacitor voltage to almost input voltage. Ideally, the capacitor voltage will never be equal to input because you have an asymptote. But you should consider your minimum/maximum voltage levels which your circuitry consider to be 0 or 1. So you will have a minimum square wave fundamental frequency that can make your capacitor output to vary between 0 and 1 (for a given RC).
Best Answer
Well the lowest voltage on the output cannot be less than 11.3 volts (one diode drop from 12V) and given that your 19 volt p-p square wave attaches itself to the output when the lowest point hits 11.3 volts, the final output has to range from 11.3 volts to 19 volts higher at 30.3 volts.
Virtually same answer as you - just a difference in what I assumed the forward volt drop of the diode to be. Given that the square wave is 50 MHz the 100k pull down resistor might reduce the peak output by around a milli volt or so.
Also no problem with the capacitor at 50MHz - it'll sail straight through. Given that the diode is really fast you won't get much of an issue with the diode's reverse recovery time response.