The jitter mentioned in the datasheet (p. 25) only applies to CLK pin jitter -- using the start pin to determine sampling frequency doesn't effect CLK pin jitter.
The difficult part of setting "a sampling frequency of about 1kHz to 1MHz" is adjusting the analog antialiasing filter that drives the input of the ADC.
(While that filter is difficult for sigma-delta ADCs, it's even more difficult for SAR ADCs and every other kind of ADC).
So I'll gloss over that and skip to the easy part of setting "a sampling frequency of about 1kHz to 1MHz":
If you are lucky, there's a timer/counter in your microcontroller that you can set up to drive a pulse out some pin at a programmable rate.
If you are not so lucky, there are many off-the-shelf timer/counter chips with such a pulse output pin; connect that chip between your microcontroller and the ADC in such a way as to allow the microcontroller to adjust the pulse rate on the fly.
In your place, I would consider the following options:
Option A: variable-frequency CLK.
I might connect that programmable-frequency output pin to the CLK input of the ADS1675.
Then set the start pin to +3V to select "multiple conversion" mode to automatically generate a series of conversions at several rates given in the datasheet (p. 17).
To get 1 megasample/second (1 MS/s) in this arrangement apparently requires pulses at exactly 8 MHz.
(Alas, many timer/counters can't go that fast).
Option B: fixed-frequency CLK, variable sample rate.
I might connect that programmable-frequency output pin to the start input of the ADS1675, using "single conversion" mode to generate a single new conversion at each pulse (p. 17).
To get 1 megasample/second (1 MS/s) in this arrangement requires pulses on the start pin at exactly 1 MHz,
and a fixed-frequency oscillator driving the CLK pin at anywhere from 8 MHz to 32 MHz -- perhaps something easily generated from the 72MHz clock you're already using.
(Alas, this approach is most vulnerable to aliasing).
The datasheet (p. 25) also says
"It is recommended that the START pin be aligned to the falling edge
of CLK to ensure proper synchronization because the START signal is
internally latched by the ADS1675 on the rising edge of CLK."
so I would set up the timer/counter input CLK to be driven by the same thing driving the ADS1675 CLK.
Option C: fixed sampling rate.
I might connect the ADS1675 to sample at some fixed sample rate (perhaps 1 MS/s or 2 MS/s or 4 MS/s).
Perhaps the simplest way to do this is to drive the CLK pin with a fixed frequency crystal oscillator (8 MHz or 16 MHz or 32 MHz), set the start pin to +3V to select "multiple conversion" mode, and set SCLK_SEL to GND to select "Internal SCLK" mode.
Then set up the microcontroller as a "SPI slave" to receive the data.
Then once I have data in RAM, use software to decimate or average or otherwise generate a series of values at a slower sampling rate.
(Because it has a fixed hardware sampling rate, this approach has the simplest anti-aliasing filter, and doesn't require timer/counter hardware).
(Alas, this approach uses the most power).
In all likelihood, the ADC will: -
- Sample the signal
- Convert the signal
- Feed out the digital representation of the signal
- Repeat
This means the latency is approximately the time between consecutive samples. More sophisticated ADCs could be (or can be) sampling the input signal whilst feeding out the digital value of the previous sample but, given that sampling is usually quite short I'd say you can use the inter-sampling time as the latency.
Best Answer
As far as first-order effects are concerned, it doesn't really matter.
However, second-order effects, including the pickup of noise on the long traces, would suggest keeping the filters close to the ADC, where they can help suppress the effects of such noise.