LDO regulators based on P-type transistors seem to be the preferred form of linear voltage regulator today, but I keep hearing about how I have to choose the output capacitor(s) carefully to guarantee stability. The older high-dropout regulators with N-type transistors didn't seem to have this problem. What is it that causes LDOs to be less stable? Is it the P-type transistor? The smaller difference between \$V_{in}\$ and \$V_{out}\$? Both? Or something else altogether? And why is the ESR of the output capacitor so important?
Electronic – Why are low-dropout (LDO) voltage regulators unstable
control systemldostability
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Best Answer
A LDO is a control loop. And like all control loops, there is always room for instability.
So how do you make a control loop stable ?
If you we look at a typical open loop response of an LDO, it may look like this
There are a number of poles.
There is also one zero in this image.
If you look at point 2 of a stable loop, it says that the slope should be -20db/dec.
Well, what if...the zero was never there. That means that the slope when it hits 0db, is -40db (due to the two previous poles). Instability.
Adding a zero before the 0db axis, makes the system stable.
The easiest way to add a zero to the system is through the ESR of the capacitor. You need a capacitor anyways, so you are killing two birds with one stone here.
The ESR matters, because it controls the placement of the zero. It should be low enough so that you can get the -20db/dec when you cross the 0db axis but low enough that the gain is below 0 dB before the next pole (usually due to the parastics).