As far as memory cells go (SRAM/ROM/Registers) in simple chips everything i've looked at seems to use the Two-Inverter CMOS schematic (Just from readings/googling and such).
In I guess "real life" chips are Registers/ROM/etc.. created using Inverters or something different (like an SR latch…..etc…)
That being said what kind of Latch/Flip Flop are most commonly used in Computer Architecture (Like a Counter or Adder or Shift Register)?
Since there are like 8-9 different types of Latches/Flip Flops all together (I've heard JK is most 'versatile' but that doesn't necessarily mean it's used the most)
Best Answer
It is possible to construct a RAM out of flip flops and multiplexers. Such designs require a lot of silicon, but they can be very fast. Further, such designs inherently allow a RAM to any number of read ports independent from its write port and allow predictable behavior if a memory location is written and read on the same cycle (the read is guaranteed to yield old data for the duration of the cycle).
One could also construct a RAM using using a pair of inverters with pass gates on the feedback path, so that while new data was being written the circuitry performing the right would not have to fight the RAM's feedback transistors. Doing such a design "properly" in CMOS would require eight transistors for each RAM cell--a considerable improvement over using a flip flop per cell. Unfortunately, it would also require having both active-high and active-low select lines for each row.
A common approach to constructing large static RAMs is to have a pair of inverters which unconditionally feed back to each other, but have the P-channel side be "weak" enough to be overpowered by a couple of N-channel transistors (one of which may be quite big) in series with the column bus wire. This will require two column wires--each tied to one inverter through an N-channel pass transistor--but both pass transistors may be driven by a common row wire. A memory cell is written by enabling it and grounding one of the column wires. The transistor driving that wire will initially have to fight the cell's P-channel transistor, but once it has been overpowered the other side's P-channel transistor will turn on and the P-channel transistor one was fighting will switch off. The "bus contention" state will thus only exist for a moment.
Of course, once one gets into larger memories it becomes common to ditch the static-RAM architecture in favor of dynamic RAM which not only reduces each memory cell to a single transistor, but does so with a layout that ends up being more compact than almost any other layout one could do with the same number of transistors.