I am really confused with all of the ground bounce, decoupling, bypassing, filtering, resonance and ESR&ESL stuff.
What I currently understand is:
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Ground bounce occurs when the (capacitive part of the) load trying to source (and at the same time IC trying to sink) the current which has a high enough \$\dfrac{di}{dt}\$. Lead inductances of the package do not matter much, however other inductances of the traces which are bigger compared to the IC leads matter. That's why capacitor(s) are put as close as to the IC power pins to provide a spontaneous power supply that is close enough and have small path inductance enough to prevent ground bounce.
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Decoupling is the job of the capacitor mentioned above. Also, it will bypass the noisy sub-circuit from the quiet sub-circuits by preventing high currents that have \$\dfrac{di}{dt}\$ to distribute to the other parts of the board.
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Also, a decoupling capacitor will filter unwanted high or low frequency noise from the power supply by giving the noise a least inductance path to the ground.
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Resonance frequency plot of the capacitor will show us how effective it is at a frequency.
My questions are:
- If one uses 1nF, 100nF (both polyester film box type) and 10uF (electrolytic) through hole capacitors near the the power input of the PCB, like in the below layout, (s)he obviously won't be able to decouple the ICs that are far away, however will (s)he be able to suppress the noise coming from the power supply of the system? Is a 1nF, 10nF or 100nF capacitor effective for this job?
- May be the same question as above. Is putting a 1nF, a 100nF and a 10uF capacitor on the power bus of a breadboard effective?
- Can decoupling capacitors cause oscillations?
Below is a PCB I tried to lay out. It is an audio amp that is used in the buses so the +24V power supply input in the "input & output connector" is noisy. In the schematic I was given, there were lots of capacitors and an inductor (in both SMD and through-hole package, only one is populated). L1, C7, C8, C10, C9 are the components I am talking about. Are these capacitors effective by the means of first question? Also, do C10, L1 and C7 form an effective Pi filter?
Edit: Sorry, I had to remove the PCB and the schematic due to company policies. Oops!
Best Answer
There is a lot here that is difficult to cover. I'll do my best, but be aware that I am leaving things out on purpose. I simply can't cover every issue in the space and time that I have.
You have two main problems: 1. You are basing your electrical design off of old ideas and old rules-of-thumb. 2. You are over thinking things a LOT, especially given the performance of (or lack thereof) your audio amp chip. Let's go over your numbered points:
Another thing to keep in mind is that your amp chip has a typical distortion of 0.1%. This is a lot higher than any improvement you are considering. For example, doing some sort of ground-bounce analysis of your PCB might improve your distortion figure by 0.0001%. But that means that your total distortion might go from 0.1000% to 0.1001%. It just doesn't matter!
Now, let's go to your questions:
You're PCB layout is bad. The main problem is that you are using a "star-ground". Star-grounds are often the wrong thing to use. A PCB like this, where there isn't a lot of noise being generated and everything is fairly close together, a star ground doesn't provide any benefit and often harms things.
Ideally what you want is a 4-layer PCB where one inner layer is a solid ground plane, and the other inner layer is a solid power plane. This provides the absolute lowest power and ground impedance across the entire PCB. (In a moment I'll tell you what to do on a 2 layer PCB.)
What you have are a bunch of individual power/gnd traces that are relatively narrow and will have an impedance that is much higher than a solid plane. Also, the distance between different components is large. For example, the GND path from C3 to U1.3 is three times longer than it should be. Not only will this increase noise, but it increases the loop area. A larger loop area is going to increase your suseptability to external RF noise.
You have similar issues on the power traces. They are relatively narrow and long. This is going to increase the trace impedance and reduce the effectiveness of your decoupling caps.
The correct way to do the PCB layout in 2 layers is to fill the PCB with copper planes. The blue layer would have the GND plane, while the red layer the V+ plane. These planes will be "chopped up" with signal traces, of course, but you will have to carefully route those signals to minimize the negative effects of chopping up the planes.