Electronic – Are termination resistors needed for UART, I2C and SPI

Talking about signal termination is like opening a can of worms. This is a HUGE subject that is difficult to summarize in just a couple hundred words. Therefore, I won't. I am going to leave a huge amount of stuff out of this answer. But I will also give you a big warning: There is much misinformation about terminating resistors on the net. In fact, I would say that most of what's found on the net is wrong or misleading. Some day I'll write up something big and post it to my blog, but not today.

The first thing to note is that the resistor value to use for your termination must be related to your trace impedance. Most of the time the resistor value is the same as your trace impedance. If you don't know what the trace impedance is then you should figure it out. There are many online impedance calculators available. A Google search will bring up dozens more.

Most PCB traces have an impedance from 40 to 120 ohms, which is why you found that a 1k termination resistor did almost nothing and a 100-ish ohm resistor was much better.

There are many types of termination, but we can roughly put them into two categories: Source and End termination. Source termination is at the driver, end termination is at the far end. Within each category, there are many types of termination. Each type is best for different uses, with no one type good for everything.

Your termination, a single resistor to ground at the far end, is actually not a very good. In fact, it's wrong. People do it, but it isn't ideal. Ideally that resistor would go to a different power rail at half of your power rail. So if the I/O voltage is 3.3v then that resistor will not go to GND, but another power rail at half of 3.3v (a.k.a. 1.65v). The voltage regulator for this rail has to be special because it needs to source AND sink current, where most regulators only source current. Regulators that work for this use will mention something about termination in the first page of the datasheet.

The big problem with most end-termination is that they consume lots of current. There is a reason for this, but I won't go into it. For low-current use we must look at source termination. The easiest and most common form of source termination is a simple series resistor at the output of the driver. The value of this resistor is the same as the trace impedance.

Source termination works differently than end termination, but the net effect is the same. It works by controlling signal reflections, not preventing the reflections in the first place. Because of this, it only works if a driver output is feeding a single load. If there are multiple loads then something else should be done (like using end termination or multiple source termination resistors). The huge benefit of source termination is that it does not load down your driver like end termination does.

I said before that your series resistor for source termination must be located at the driver, and it must have the same value as your trace impedance. That was an oversimplification. There is one important detail to know about this. Most drivers have some resistance on it's output. That resistance is usually in the 10-30 ohm range. The sum of the output resistance and your resistor must equal your trace impedance. Let's say that your trace is 50 ohms, and your driver has 20 ohms. In this case your resistor would be 30 ohms since 30+20=50. If the datasheets do not say what the output impedance/resistance of the driver is then you can assume it to be 20 ohms-- then look at the signals on the PCB and see if it needs to be adjusted.

Another important thing: when you look at these signals on an o-scope you MUST probe at the receiver. Probing anywhere else will likely give you a distorted waveform and trick you into thinking that things are worse than they really are. Also, make sure that your ground clip is as short as possible.

Conclusion: Switch to source termination with a 33 to 50 ohm resistor and you should be fine. The usual caveats apply.

If the frequency/rise time and distance is high enough to cause issues, then yes, you need termination.

Transmission-Line Model

At 97mm longest trace I think you will probably get away without them (given results of calculations below) If you have a PCB package that handles IBIS models and board level simulation (e.g. Altium and other expensive packages), then simulate your setup and judge whether you need them from the results.

If you don't have this capability available, then you can do some rough calculations using SPICE.
I had a little mess around with LTSpice, here are the results (feel free to correct things if anyone sees an error)

If we assume:

• Your RAM input signal rise time is around 2ns
• PCB is FR4 with a Er or ~4.1
• PCB copper thickness is 1oz = 0.035mm
• Trace height above ground plane = 0.8mm
• Trace width = 0.2mm
• Trace length = 97mm
• RAM data input is 10kΩ in parallel with 5pF (capacitance from datasheet, resistance picked for a typical LVTTL input as nothing is given - the datasheet is pretty bad, for example the leakage current on p.21 is given as 10A!?)
• Driver impedance is 100Ω (taken from datasheet output high/low values and current -> Vh = Vdd - 0.4 @ 4mA, so 0.4V / 4mA = 100Ω)

Using wCalc (a transmission line calculator tool) set to microstrip mode and punching the numbers in, we get:

• Zo = 177.6Ω
• L = 642.9 pH/mm
• C = 0.0465 pF/mm
• R = 34.46 mΩ/mm
• Delay = 530.4 ps

Now if we enter these values into LTSpice using the lossy transmission line element and simulate we get:

Here is the simulation of the above circuit:

From this result, we can see with a 100 Ω output impedance we shouldn't expect any problems.

Just for interest, say we had a driver with an output impedance of 20 Ω, the result would be quite different (even at 50 Ω there is 0.7 V over/undershoot. Note that this is partly due to the 5pF input capacitance causing ringing, the overshoot at 2ns would be less with no capacitance [~3.7V], so as Kortuk points out check lumped parameters as well even if not treating as a TLine - see end):

A rule of thumb is if the delay time (time for signal to travel from driver to input) is more than 1/6th of the risetime, then we must treat the trace as a transmission line (note that some say 1/8th, some say 1/10th, which are more conservative) With a 0.525 ns delay and 2ns rise time giving 2 / 0.525 = 3.8 (<6) we have to treat it as a TLine. If we increase the rise time to 4ns -> 4 / 0.525 = 7.61 and do the same 20 Ω simulation again we get:

We can see the ringing is much less, so probably no action needs to be taken.

So to answer the question, assuming I'm close with the parameters, then it's unlikely that leaving them out will cause you problems - especially since I picked a rise/fall time of 2ns, which is faster than the LPC1788 datasheet (p.88 Tr min = 3 ns, Tfall min = 2.5 ns)
To be sure, putting a 50 Ω series resistor on each line probably wouldn't hurt.

Lumped-Component Model

As noted above, even if the line is not a transmission line we can still have ringing caused by the lumped parameters. The trace L and receiver C can cause plenty of ringing if the Q is high enough.
A rule of thumb is that in response to a perfect step input, a Q of 0.5 or less will not ring, a Q of 1 will have 16% overshoot and a Q of 2 44% overshoot.
In practice no step input is perfect, but if the signal step has significant energy above the LC resonant frequency then there will be ringing.

So for our 20 Ω driver impedance example, if we just treat the line as a lumped circuit, the Q will be:

\$ Q = \dfrac{\sqrt{\dfrac{L}{C}}}{Rs} = \dfrac{\sqrt{\dfrac{62.36 nH}{9.511 pF}}}{20 \Omega} = 4.05 \$

(Capacitance is 5pF input capacitance + line capacitance - line resistance ignored)

The response to a perfect step input will be:

\$ V_{overshoot} = 3.3 V \cdot e^{-\dfrac{\pi}{\sqrt{ (4 \cdot Q^2) - 1}} } = 2.23 V \$

So the worst case overshoot peak will be 3.3V + 2.23V = ~5.5V

For a rise time of 2 ns, we need to calculate the LC resonant frequency and the spectral energy above this due to the risetime:

Ringing frequency = 1 / (2PI * sqrt(LC)) = 1 / (2PI * sqrt(62.36nH * 9.511pF)) = 206MHz

Ringing frequency = \$ \dfrac{1}{2 \pi \cdot \sqrt{LC}} = \dfrac{1}{2 \pi \cdot \sqrt{62.36nH \cdot 9.511pF}} \$ = 206MHz

A risetime of 2 ns has significant energy below the (rule of thumb) "knee" frequency , which is:

0.5 / Tr = 0.5 / 2 ns = 250 MHz, which is above the ringing frequency calculated above.

With a knee frequency of exactly the ringing frequency, the overshoot will be around half that of the perfect step input, so at ~1.2 times the knee frequency we're probably looking at around 0.7 of the perfect step response:

So 0.7 * 2.23 V = ~1.6 V

Estimated overshoot peak with 2 ns risetime = 3.3 V + 1.6 V = 4.9 V

The solution is to reduce the Q to 0.5, which corresponds to a \$\dfrac{\sqrt{\dfrac{L}{C}}}{0.5} \$ = 162 Ω resistance (160 Ω will do).
With the 100 Ω driver resistance from above, this would mean a 60 Ω series resistor (hence the "adding a 50 Ω series resistor wouldn't hurt" above)

Simulations:

Perfect Step Simulation:

2 ns Risetime Simulation:

Solution (with 100 Ω Rdrv + 60 Ω series resistor = 160 Ω total R1 added):

We can see adding the 160 Ω resistor produces the 0 V overshoot critically damped response expected.

The above calculations are based on rules of thumb and are not utterly exact, but should get close enough in most cases. The excellent book "High Speed Digital Design" by Jonhson and Graham is an excellent reference for these kind of calculations and much more (read the NEWCO example chapter for similar to the above, but better - much of the above was based on knowledge from this book)