Looks good and you may just get lucky with that layout.
Being an engineer, luck is usually not a method I rely on :-) So let me show you what I would do:
1) Define the PCB stackup. Looks like you are on a 4-layer stackup, but we need to know material and thickness of laminate/prepreg etc.
2) Calculate trace widths to give you 50R on all layers. Your traces looks wide, but you didn't give your stackup so they may be okay. I would worry a bit about crosstalk though if those traces really are 50R (because I then know that they are far from your reference plane, which increases crosstalk).
3) Engineer a great low impedance power delivery network (PDN). I read between the lines that you have two planes for power and ground - which is a really good idea. I would use my tool at pdntool.com to select the right capacitor combination. And use the knowledge that bypass capacitor location is fairly unimportant. So the caps would be placed last so the don't interfere with the routing.
4) Repeat this for your Vtt supply. The termination voltage is being constantly pulled in both directions, so it needs a low impedance as well. With DDR1 on a low layer count board, Vtt ripple is a common problem (and make sure Vref is not connected to Vtt!!!). This would usually require a Vtt island with sufficient bypass. Remember about half the ripple on Vtt will be present as noise on top of any input signal terminated to Vtt.
5) Do some quick IBIS simulations to find a trace separation that gives you acceptable crosstalk. Use Hyperlynx, SigXplorer or some such tool for this. Or get someone to do it for you.
6) Do your timing analysis to find the acceptable tolerance on trace length matching (don't overdo length matching - just keep within your calculated tolerance).
7) Document the above in a nice document and call a peer review - this is a great time to find errors. You could also post that here and ask for problems in your reasoning.
8) Enter everything as routing rules in your CAD tool and do that layout. Remember with a well engineered PDN and 50R on all layers your via count is irrelevant. Also if you just route your differential clock as two 50R traces of same length (within half a rise-time or so), you need not treat them special.
For inspiration you can also look at the layout examples on the JEDEC website.
Hope this helps - feel free to ask more questions.
First off, the second one looks absolutely horrid. Don't do that.
Secondly, you should always envelop the actual drill with the trace, whether you need to make the trace large enough to envelop the thermals of the copper via is more a result as to how much current your trace will be carrying.
Best Answer
Ground Ring
Surrounding the PCB, and sometimes areas within the PCB, is surrounded by a ring of traces that is connected to GND. That ring exists on all PCB layers and is connected together with a bunch of vias.
To explain what this does, I need to describe what happens when you don't have the ground ring. Let's say that on Layer 2 you have a ground plane. On layer 1 you have a signal trace that goes all the way to the edge of the ground plane, and runs for several inches along the edge. This signal trace is technically directly over the ground plane, but right at the edge. In this case that trace will radiate more EMI than other traces, also the trace impedance would not be as well controlled. Simply moving the trace in, so it is not at the edge of the ground plane, will fix the problem. The more "in" you move it the better, but most PCB designers will move it in at least 0.050 inches.
There are similar issues when you have a power plane. The power plane should be moved back from the edge of the GND plane.
Enforcing these rules, that traces can't be within 0.050" of the edge of a plane, is difficult in most PCB software packages. It's not impossible, but most PCB designers are lazy and don't want to set up these complicated rules. Plus, this means that there are areas of the PCB that are simply empty of useful traces.
A solution to this is to put in a ground ring and tie it all together with vias. This will automatically prevent other signals from going into that area of the PCB, but also provide better EMI prevention than simply moving the traces back. For the power plane, this also forces the power plane back from the edge (since you just put a GND trace there).
Mounting Holes
In most cases you want to connect your mounting holes to GND. This is for EMI and ESD reasons. However, the screws are really bad for PCB's. Let's say that you have a normal plated through hole that is connected to your ground plane. The screw itself can destroy the plating inside the hole. The screw head can destroy the pad on the surface of the PCB. And the crushing force can destroy the GND plane near the screw. The odds of any of this happening is rare, but many EE's have had enough problems with this to come up with fixes.
(I should note that destroying the plating and/or the pad usually results in metal flecks getting loose and shorting out something important.)
The fix is this: Add vias around the mounting hole to connect the pads to the GND plane. Multiple vias gives you some redundancy and reduces the inductance/impedance of the whole thing. Since the via is not under the screw-head it is less likely to get crushed. The mounting hole can then be unplated, reducing the chance of loose metal flakes shorting something out.
This technique is not foolproof, but does work better than a simple plated mounting hole. It seems like every PCB designer has a different method for doing this, but the basic thinking behind it is mostly the same.