Electronic – Assigning the different value to parameters in Generate block in Verilog

I want to instantiate a module having parameters using generate block. But I want to assign different values to parameter for different instantiation of the module.

For example:

This is my module that I want to instantiate and it has parameters DATA_WIDTH & SIZE_WIDTH .

module gen_module (
     input clk,
     input rst );

     parameter [3:0] DATA_WIDTH = 1;
     parameter [3:0] SIZE_WIDTH = 2;

endmodule

This is another module in which I am instantiating gen_module using generate statement. (But here I am using only one parameter value of D_WIDTH and S_WIDTH for all instantiation )

[It is working but with single value for all]

module top_module ();

    wire clk;
    wire rst;

    parameter N = 5;
    parameter [3:0] D_WIDTH = 7;
    parameter [3:0] S_WIDTH = 4;

    genvar j;

    generate
        for(j = 0; j <= N; j=j+1) begin : GEN_BLOCK
           gen_module #(.DATA_WIDTH(D_WIDTH), .SIZE_WIDTH(S_WIDTH)) i_gen_module (
             .clk (clk),
             .rst (rst)
          );

        end
    endgenerate 
endmodule

But I want to do something like this statement. (As I know parameter array is not applicable in Verilog)

gen_module #(.DATA_WIDTH(D_WIDTH[j]), .SIZE_WIDTH(S_WIDTH[j])) i_gen_module (

Here I want to give different values to D_WIDTH[j] & S_WIDTH[j] and want to use them to assign to parameters (DATA_WIDTH & SIZE_WIDTH) in generate block.

[Here J will change with for loop]