I am designing an FPGA that will include state machines and counters both of which needs to be reset, i have heard that it was always better to use synchronous resets, is it true?
I am not sure that my synchronous state machine works:
What will be the difference if i use synchronous or asynchronous resets?
Electronic – Asynchronous reset
fpgareset
Related Solutions
There seem to be a lot of views on this one.
Asynchronous assertion, synchronous deassertion is said to be good practice. This avoids the issue of the clock not running (or running too slowly to capture the reset signal) on synchronous assertion, and possible metastability on asynchronous deassertion.
You would use a reset synchroniser (two FFs) with the output tied to the rest of the designs resets:
Couple of discussions:
Async and sync reset
Letters On Sync vs. Async Resets
If I have a design with synchronous reset, and you feed it with an async reset signal which may be asserted at any time, it internally goes via a clocked flip-flop. So for the design, it will be just like a synchronous reset. So it has to work.
Best Answer
The problem with asynchronous resets is that you need to avoid metastability, which happens when the timing constraints are violated. In particular you need to ensure the input signal is stable for the required setup time before the clock edge can occur, illustrated in the diagram:
where C2 is your clock and A is your flip-flop input.
An FPGA logic unit has a form like this:
When you de-assert the reset signal the input to the flip-flop changes from the reset value to the next value. If the clock edge occurs sooner than the setup time requirement, you will get a timing violation. Similarly you can get a hold time violation, if the de-assert occurs just after the clock edge.
This is why you need to ensure that there is a sufficient interval between the clock edge and the reset de-assert. A straight forward way to do this is to use a synchronous reset de-assert or a fully synchronous reset.