Atmel has very clear application note about increasing ADC resolution by oversampling with sources in C.
Description in PDF is here, sources are on Atmel website.
What is the ADC Clock?
The section that you are seeing is for the clock used for the ADC. This clock is not directly related to the max sampling frequency though. The clock is what is actually being fed to the ADC module which needs to be faster than your sampling so that it can handle some magic for you.
How does the Max clock relate to the max sampling frequency?
What the datasheet is saying is that in order to get 10 bit resolution your clock can not be any faster than 200 KHz. When your clock is at that speed, you will be able to sample your signal at 15,000 samples per second.
If you don't need all 10 bits of resolution then you can provide the ADC with a faster clock and you will get a faster sampling rate, but the datasheet is not clear as to how fast you can go and still get 8 bit resolution.
I would assume that the clock to sample rate ratio is fixed, so 200K/15K = 13.33 which means you can go as low as 50 KHz clock resulting in 3.75 kSPS.
Why a minimum clock to get a 10 bit sample?
The ADC module is doing a sample and hold in which the voltage is essentially held in a capacitor. If you slow the clock down too much, the voltage can start to bleed off of the capacitor before a complete sample is performed. This change in voltage makes it such that you can't get all 10 bits accurately.
So what does this all mean?
According the the Nyquist-Shannon sampling theorem your sampling frequency needs to be at least twice the maximum frequency in your signal. You can learn more about why by looking at this question: Puzzled by Nyquist frequency
So in order to get 10 bits of resolution, the max your signal can be is 7.5 KHz, but if you need to sample a signal faster than that, you can, but the datasheet does not mention how high you can go or how much it hurts your resolution.
Best Answer
The maximal frequency of the ADC is specified as 1MHz.
The actual problem is not exactly the ADC itself, but the sample and hold device, that in the first 2 clocks of the ADC have to get a sample of the input voltage.
When these 2 clocks are two short, the storage capacitor of the S/H is not able to follow the input signal with sufficient accuracy.
BTW, that is why there is minimal frequency as well. In this case, the huge conversion time allows the storage capacitor to discharge during the conversion.
On 1MHz clock, you will get 13us conversion time or approximately 77ksps. On 200kHz clock - 15ksps.