In Sedra and Smith: Microelectronics Circuits (6E), it is mentioned, on page 185:
Recalling that the CBJ is much larger than the EBJ, the forward-voltage drop \$v_{BC}\$ will be smaller than \$v_{BE}\$ resulting in a collector-emitter voltage, \$v_{CE}\$, of 0.1 V to 0.3 V.
Why does a difference in junction area causes a change in the forward-voltage drop? A similar question was asked on the site, however, it did not help.
So, I tried using Ebers-Moll model and that is where I am actually getting stuck. So, my question is this:
How should I apply Ebers-Moll method for a transistor working in a saturation region, to get the equation for \$V_{ce}\$?
So far, I know that there are three major Ebers-Moll models, here. I also read that the \$I_{s}\$ is a property of the emitter-base junction.
Additionally, \$i_{c} \leq \beta i_{b}\$.
Thank you for your time. Please inform me if some additional information is needed.
Best Answer
There is no formula for Vce(sat) because this bulk resistance is process dependent. The chip size, doping, layered etching methods all are factors.
You must refer to the Vce(sat) parametric model or datasheet for this property.
Diodes Inc (nee Zetex) has many of the earliest process patents of ultra-low Vce(sat) at high currents. They were also the first to characterize this as Rce, a linear resistance, in datasheets.
This collector-emitter saturation bulk resistance called \$R_{CE}\$ is defined for Vce=Vce(sat) at Ic/Ib=10 at various currents. In some cases, the log-log, or linear graph of Ic vs Vce shows the linear property above 10% of Imax.
example of Rce p.2 of 5 SOT-23
Prior to Zetex, you had to get a big power transistor in TO-3 can to get this low value of ~Vce(sat)/Ic.
Equivalent On-Resistance Rce(SAT) 35m typ 50 mΩ max. @Ie = 2A, Ib = 200mA
I have often referred to bulk resistance in diodes as ESR and this property is always inversely related to package power rating ( and thus chip size) as a designer's figure of merit (FoM). This property exists for all diodes and LEDs.