I have a penta-band GSM transciever on a 4-layer board, along with a matched chip antenna. Similar concept to EE.SX/questions/35836/how-do-components-on-a-ground-plane-of-monopole-pcb-antenna-effect-radiation-eff.
First few prototypes placed most discretes on the bottom side, and that worked well. Now I've optimized things and want to put most discretes on the top for DFM assembly.
Question is, even with a top side ground plane, how much trouble is this asking for?
Size is fairly small, 4×3 inches. If no (>\$\frac{\lambda}{10}\$) traces are exposed, is it much of a concern?
How is such a proposition approached? Are there any rules-of-thumb for "exposing" areas of ground plane to minimize RF induction in component leads?
Or grouping / separating to avoid critical lengths?
How about a vertical metal shield strip or fence, the same height as the chip antenna, soldered into the PCB some distance away?
Would that eliminate EMI concerns beyond the strip?
Best Answer
With EMI\EMC it is more of an art. Your entire design would have to be considered. A rule I use is, EMI will take the lowest inductance pathway to return to ground. Increase the inductance and the radiation will be attenuated.
If price isn't a consideration and you know it's a problem, put a shield on the part of the PCB you are worried about. There is a book that is a great reference and it has an entire chapter on shields and a section (6.16) on board level shields and a small bit on fences. You could always try a shield or a fence, but it will take some experimentation. It can be wise to devise several options that you can use to mitigate noise, test them out and see what works.