I'm not sure about at which stage do the address computation take place at each of the versions of the risc-v?
I just wanted to make sure i got that right-
Single-cycle risc-v: Branch target address computation happens at Execute stage
multi-cycle risc-v: Branch target address computation happens at Decode stage
Pipeline risc-v: Branch target address computation happens at Execute stage
Thank you!
Best Answer
The branch address is the signal PCBranch.
Instruction Fetch
Instruction Decode
Execute (ALU)
Memory
Write Back
The complete pipelined MIPS is on the following image
The address is calculated in the Execute stage but taken in Memory stage.