I'm trying to build a framebuffer using an FPGA and an external memory. I have a soft core CPU running on the FPGA as well a small chunk of logic to output signals to an LCD. My goal is to have the CPU rendering/writing a frame to a small chunk of external memory and then have the LCD write module read from that external memory.
My issue is that the LCD and write code is on a crystal–>PLL at 9Mhz and the CPU is on the original crystal at 50Mhz. Do I have to put the CPU on the PLL as well or is there a way of interfacing the logic in such a way that it will work as is?
Specs:
Memory => SDRAM @ ???Mhz
CPU => NIOS II @ 50Mhz
LCD => Sharp 480×272 @ 9Mhz
FPGA => Cyclone III
Best Answer
You'd have to set up synchronization registers across the clock boundaries. And as the clocks are out of phase with each others, there's always the possibility of metastability, but I suppose the FPGAs are not very susceptible to metastability.
I would suggest to run your CPU at some "easy" multiple of 9 MHz, perhaps 9 x 4 = 36 MHz or 9 x 8 = 72 Mhz and divide the 9 MHz clock to the LCD from there. It would be much easier and reliable. The clocks would be phase aligned with each other; no possibility of metastability, ever, and normal synchronous design rules could be used. I'd suggest that you consider it.