Electronic – Can ground plane EMIT noise

emfground-planegroundingnoisepcb-design

I have 3 separate grounds in my project:

  • AGND – Analog ground is very quiet, very small relatively smooth currents
  • PGND – Power ground used for power bypass caps and power supply related circuitry is less quiet
  • DGND – Dirty ground for digtal, led drivers, relays and things that cause horrible fast transient spikes and high current spikes

These grounds run over separate traces / wires back to a "star" on the power supply board.

Q: If I make a ground plane area that is DGND (the "dirty" ground), is that more or less likely to emit noise that could be picked up by surrounding circuitry as opposed to making the DGND circuitry regular traces and using another ground like PGND for the ground plane?

Generally we think of ground as being a low noise low impedance path. But if it's actually really noisy like a "dirty" ground that can see enough current to cause 100 mV spikes relative to a regular "quiet" ground, is that suitable for a ground plane or will putting noise into a big plane cause more harm than good?

Best Answer

The spiking that you are seeing on the ground plane is actually a voltage difference due to current running through the return path from your driver. Large, high speed changes in current create a voltage difference for various points in the return path due to its inductance. To keep the noise from bleeding over into your other circuitry, you can try the following approaches:

  • Do not place the dirty ground plane in places where there is no current path. A common error is to make this ground plane the entire board area. This creates a large capacitor plate in areas where there is no current, and non-current-carrying portions of the ground plane have the voltage spikes from the adjacent current path.

  • Keep the quiet stuff and their traces away from this ground plane. Traces on a separate layer can be capacitively coupled to the plane.

  • Watch out for loops. Your current path to and from the devices with the high frequency, high current ideally should be close together and parallel to reduce the loop area and associated induced voltages. Best to have the power going out and coming back from your source be close together and parallel to the extent possible.

  • Keep the high current runs short.

Hope this helps.