As part of MIPS design we have something called as register file. It only has 32 registers each 32 bit which only makes 1024 bits or 128 bytes. I am not sure how to tell Quartus to instantiate this as a memory block with 2 read ports and 1 write port. The Dual Port RAM in Quartus seems to be having 2 read/write ports. It is not possible to have 2 read and 1 write port. How do I create a 2 read port + 1 write port memory using the memory blocks in Altera Quartus II?
Electronic – Can one instantiate RAM with 2 read ports and 1 write port as IP in Quartus
memoryquartus-iiram
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Best Answer
There's a trick for doing this in Xilinx technologies : instantiate two memory blocks, with their Write ports tied together. (Each block is configured to have 1 read and 1 write port, independently addressable).
I can see no reason why the same pattern wouldn't work in Altera FPGAs. Last time I looked, their memory blocks had similar dual-port (just not 3-port!) capability.