I'm a student trying to learn Verilog on my own with a dev board. This is just a simple and short module. I just need some clarifications.
module BASIC (CLOCK_50, KEY, LEDG);
input CLOCK_50;
input [3:0] KEY;
output reg [8:0] LEDG;
reg [2:0] key0_dly;
always @(posedge CLOCK_50)
begin
if (!key0_dly[2] && key0_dly[1])
LEDG[0] <= ~LEDG[0];
key0_dly <= {key0_dly[1:0], KEY[0]};
end
endmodule
now I know the basic syntax of Verilog. My questions would be:
-
What is the purpose of key0_dly? Why does the if statement check the 2 bits of it?
-
Why is key0_dly assigned the values
{key0_dly[1:0], KEY[0]}
? What does that line do? -
Is this line
key0_dly <= {key0_dly[1:0], KEY[0]};
in the if statement? Am I correct in saying that if there is no begin and end then like in C only the one line of code that follows in the if block?
Best Answer
It wants to complement
LEDG[0]
only if the trigger has occurred during the previous loop but not 2 loops ago. Looks like simple debouncing/edge detection to me.It left-shifts
key0_dly
one bit, shifting the value ofKEY[0]
in.Sounds right. But you need the shift to happen each loop otherwise there will be no way to trigger the condition.