Electronic – Can the CMOS 4014b be used as a SIPO shift register

You should not have a problem using a 16 bit shift register (or two chained 8 bit shift registers similar to the 74HC589A).

There are two ways that you could consider to ignore the unused 6 bits: 1) shift all 16 bits and mask the unused bits in software, or 2) only shift 10 bits across the serial connection.

If you are reading the data using the built-in SPI peripieral on some microcontrollers, you may have to shift in a multiple of 8 bits per word, which would force you into scenario 1. Otherwise, it may be simpler to implement scenario 2.

Most shift registers don't care if you don't shift all the bits... they will happily accept new data on the parallel load clock regardless of how many bits have been shifted. If you only plan to shift 10 bits, make sure to use the bits that will be shifted out of the register first.

In either case, you should tie the unused input pins to your supply rail or ground through a resistor, as floating inputs can cause problems on some ICs.

Your idea about programmatically setting the clock and data pins is correct. This technique is often called 'bit-banging'. To find out what goes wrong you should post your code.

The 5V / 3.3V issue could very well be your problem. Try to power the HC595's from 3.3V to see how that affects the problem.

The chip in the RaPi has some dedicated hardware that can be used to interface to SPI peripheral like the HC595. But unless you need to shift data out at the maximum speed the use of such a peripheral is not worth the trouble: bit-banging is much easier.

PS you talk about the clock and data pins, are you aware that there is a second clock (hold clock) that you must pulse once per transferred byte, and that there are a few other pins (reset, enable) that must also be kept at the appropriate level?