Electronic – Carry-lookahead adder – what happens to carry bit

If the ripple-carry adder is fewer gates and satisfies timing constraints, why should the synthesizer not prefer it? In many cases, the most efficient way to generate a carry chain is to use a mixture of ripple-carry and lookahead units. For example, if one is implementing a 32-bit adder with a 16-gate-delay timing budget, rendering it as two eleven-bit sections and a ten-bit section may require fewer gates than the fastest possible arrangement while still meeting the timing requirements.

I'd suggest figuring out how to play with timing constraints; I would guess you'd find that independent of whether you design in a ripple-carry or carry-lookahead adder, the mix of ripple- and lookahead-carry generated by the compiler would vary with the constraints specified. If you wish to maintain a particular arrangement of carry logic, you can explicitly tell the compiler that you want certain signals generated (since this is a fictional design anyway, routing them to I/O pins might be a good way to do that). I suppose a compiler might still decide to ignore the P and G signals even if it was forced to generate them, but hopefully it would be smart enough not to do that.

It can help to add intermediate states to the truth table; there are a lot of letters from the alphabet you haven't used :-). Name the output of the first XOR gate D and add a D column to the truth table. You may want to have clearly separated "inputs", "intermediate" and "outputs". I separate them with a vertical line, and fill out the combinations for the inputs. You have three of those, that's eight combinations.

Then fill out column D, which takes A and B as inputs. Even if there were 15 more inputs, ignore them; only A and B are relevant. Work gate per gate, divide and conquer. When you've finished column D you can fill out column S in the "outputs" section, because that only depends on D and Cin, and you have those.

Repeat for the outputs of the AND gates: add E and F to the "intermediates" section, and fill them out only looking at the columns which are input for each gate.