In my first layout, with a 9.2k load I get a gain of ~55 (20mVpp in -> ~ 1.1Vpp out).
My current understand is that if I replace the resistor load with something else that presents as 9.2k (i.e. the Rin of the circuit) it should have the same gain. So I connected ALTload in its place (a copy of the same BJT amplifier circuit that has an Rin of 9.2k) but don't see what I was expecting at the same point in the circuit (after C3).
Can anyone guide me on what was flawed in my assumption/implementation?
- It looks like the gain increased – Why?
- What's causing the top peak to flatten out – Has it got something to do with the voltage dividor R5/R6 sets the upper limit @ 4.174V? I thought capacitor C3 would 'reset' the DC offset and the 1.1Vpp would be 4.174V +/1 0.55V?
Many thanks in advance
FYI – I largely followed the the example here (pg 10/slide 19): Small Signal Model
I ran this simulation to find the Rin ~ matches what I expected:
What is meant by 'highly non-linear for many reasons` – Perhaps there are certain topics/concepts I can go and read up on in more detail to better grasp this?