Electronic – Changing pin direction without glitching on LPC800

cortex-mglitchgpiolpc

I'm looking at an LPC812 Cortex M0+ microcontroller and its GPIO functions. On a PIC microcontroller, one would always set the LATch prior to changing the direction of a given pin. This avoids the possibly nasty situation where a pin "gitches". ie: the output state of the pin is a 1 just before you change direction and set it to a 0. This results in a pin output changing from 1 to 0 over a sub-microsecond duration.
(related: Why set PORTx before TRISx?)

However, it is not obvious from the user manual (UM10601) whether writing a value to a pin which is currently an input has any logical effect (it will not have a physical effect on the pin state as it's an input). Thus if I write a zero to PIN0 (page 92/93) that should in theory clear all the output bits. If they were latched, which isn't certain.

Section 7.7.2 says that "If either or both of these conditions (ie: set to gpio and set to output) is (are) not met, writing to the pin has no effect.". Which isn't helpful as I know there's no physical effect.

Under the IOCON description (6.3, page 68) is the following Remark:

If the open-drain pins PIO0_10 and PIO0_11 are not available on the package, prevent the pins from internally floating as follows: Set bits 10 and 11 in the GPIO DIR0 register to 1 to enable the output driver and write 1 to bits 10 and 11 in the GPIO CLR0 register to drive the outputs LOW internally.

In my opinion this is an incorrect sequence (unless the GPIO port outputs defaults to low, something else that isn't documented). On a PIC16 I would set the HI/LO state first, then change the direction.

I admit that if the part had arrived I would just test this on the bench. However I'll put this on stackexchange as I'm seeing examples everywhere which set direction and then the value, all of which may be glitching output pins.

Best Answer

You're over-analysing this. There are two registers involved in a GPIO pin, the output data register, and the direction register. Both of these are writable at any time (and I agree your Section 7.7.2 quote does not make this super-clear.)

The remark on p68 doesn't care about a transition, it cares about a power-optimised stable end state. Changing the order makes no real difference, but is cleaner as you describe.

There is no changing from 1 to 0 over a sub-microsecond duration. When you enable the output, it takes the driven value in just the same way as if you drive it from 1 to 0 using the data value.

It is only when the reset data value is 0, the tri-state is pulled up, and after enabling the output you write 1 to the data pin that you would see a pulse.

All peripherals are different, but for example

A read from GPIODATA returns the last bit value written if the respective pins are configured as output, or it returns the value on the corresponding input GPIN bit when these are configured as inputs. All bits are cleared by a reset.

Specifically, the last write and not the last write whilst the pin direction was set as output.