I have a project involving an ADC sampling at 500 MHz. I need to take this ADC data and boil it down into something a cheap CPU can process. I believe this is a good application for a low-grade FPGA, so I am trying to understand how best to approach selecting a specific FPGA device.
The math involved in the FPGA will be minimal. Basically, I need the 500 MHz sampling speed to capture the physical event, but the FPGA will be selectively discarding most of the samples. So I don't think I care about how many LUTs, cells, or RAM bits the FPGA has. I need relatively fast I/O, and I need it to be cheap.
How can I tell if one of the cheap FPGAs (example: Spartan-6) I'm looking at is fast enough to keep up with my ADC? For the purposes of the this question, assume the ADC has an LVDS connection. Two ADC chips I am considering are the AD9434 and the ADS5403. I'm trying to understand the minimum requirements to interface with an ADC of this caliber.
What dictates the limit on an FPGA's I/O communication speed?
What are the key datasheet parameters I should be paying attention to when looking for an appropriate part?
Note that this is an embedded application, so stringing together some dev boards can be effective to prove out chip performance, but ultimately this will be a custom design.
Also note that the final sampling speed for future work may differ, so I am interested in understanding and comparing key I/O parameters between FPGAs in general. Other applications may require 250MHz sampling, or 1GHz, or 1.5GHz. I want to understand the FPGA I/O bottlenecks so I can choose a cost-effective FPGA for whatever sampling speed may be required.
There are many factors that determine how fast logic can run in an FPGA, most of the time you won't know until you put logic on the FPGA because the delays in the logic determine how fast the logic can operate. The way to check is the datasheet of each device, which is tedious. One thing for sure is no logic will run faster than the clock speed of the FPGA, and the logic will always run a bit slower (because of cascaded gate delays).
The most important one would be the I/O that the ADC uses, high speed ADC's use trancievers most of the time, you'll need to make sure the transciever operates faster than the rate of the ADC, for example the spartian 6 datasheet has info on how fast the LVDS transceivers can operate:
Source: DS162 datasheet
Make sure you have the right equipment before attempting a very high speed design, you'll need at minimum a differential probe that runs 2x the frequency of your fastest I/O speed for troubleshooting. Make sure you know how to impedance match the traces. If you've never done high speed, I would not cut your teeth on this type of design unless you have a consultant or someone who has done it before around. If this is your first go around, and your running low quantity, I would buy an eval board and use that.
Another thing is there might be better ways to make your measurement than a 500MHz ADC, something like an SDR can go well past 500Mhz and be better for your application depending on the bandwidth