Lets see what we're trying to implement here:

- AC follower (A = 1 for frequencies of interest)
- AC coupled (A = 0 for DC)
- High input impedance

We get the desired results by the following means :

- AC follower - \$V_{out}\$ and \$V_-\$ are shorted
- AC coupled - a series capacitor after \$V_{in}\$
- High \$Z_{in}\$ - bootstrapping

From the first glance it looks like \$Z_{in}=2M\$. Well, you could achieve the same without bootstrapping, so why bother? It turns out that the input impedance of this follower is higher than 2M. In fact, the input impedance in this configuration will (usually) be determined by amplifier's input impedance, and not by the values of voltage divider resistors.

**Lets see how it works:**

DC is blocked, therefore all the signals in this explanation are AC at the frequencies of interest.

Step-by-step propagation of signals:

- \$v_{in}\$ changes -> \$v_+\$ changes
- \$v_+\$ changes -> \$v_{out}\$ changes
- \$v_{out}\$ changes -> \$v_-\$ changes
- \$v_-\$ changes -> \$v_{out}\$ changes -> back to step #3 above

The only possible steady state in this condition is: \$v_+ = v_- = v_{out}\$.

Up until now I described the basic follower. However, in this configuration there is one addition - \$v_-\$ is also fed back to the upper resistor's second terminal (lets call this resistor \$R_1\$). So, what the voltage at the resistor will be then? In terms of amplifier's inputs it will be:
$$v_{R_1} = v_+ - v_-$$
From the above discussion you may think that this voltage will be zero, but let's not forget that the above discussion is the idealized case. In fact, the gain of the follower won't be exactly 1 - it will be very close to 1, but not 1. What are the implications of this? Well, the voltage on the resistor will be:
$$V_{R_1}=v_+ - v_-=v_{in}-Av_{in}=(1-A)v_{in}$$
Since A is very close to unity, the voltage on the resistor will be almost zero, but not zero. This voltage will give rise to current of magnitude:
$$I_{R_1}=\frac{(1-A)v_{in}}{R_1}$$
What is this current? It is a current drawn from the source by the resistive divider! If we try to express the "effective resistance" of the divider by comparing the above equation to Ohm's law, we will get:
$$R_{eff_{divider}} = \frac{R_1}{(1-A)} >> R_1$$
Given that this huge effective resistance of the divider is in parallel to the input impedance of the amplifier (which is big, but not that big), you can understand why the input resistance of the whole circuit will be determined by the latter.

**An answer:**
You may notice that I did not answer your question yet. Well, the answer to your question is that a tiny current source is just a way of modeling the tiny current which will flow trough \$R_1\$. It is not really zero, but very close to it. Don't take this too seriously - if you understood the whole explanation I wrote above, don't care about not understanding some alternative (and useless in my opinion) way of describing this circuit.

^{simulate this circuit – Schematic created using CircuitLab}

Note 1: The input voltages are only \$V_{cc}\$ and \$V_\text{High Voltage}\$. You don't apply anything at the \$V_{BS}\$ node. It is only for representation.

Note 2: Notice that there are two different type of grounds. Those grounds must not be directly connected to each other.

You must drive the MOSFET between its gate and source terminals. Since the source terminal voltage of a high side MOSFET will be floating, you need a separate voltage supply (VBS: \$V_\text{Boot Strap}\$) for the gate drive circuit.

In the schematic below, VCC is the voltage source of the rest of the circuit. When the MOSFET is off, ground of the boot strap circuit is connected to the circuit ground, thus C1 and C2 charge up to the level of Vcc. When the input signal arrives to turn the MOSFET on, ground of the gate drive circuit rises up to the drain voltage of the MOSFET. The D1 diode will block this high voltage, so the C1 and C2 will supply the driving circuit during the on-time. Once the MOSFET is off again, C1 and C2 replenish their lost charges from VCC.

Design criteria:

- RB must be chosen as low as possible that will not damage D1.
- Capacity of C2 must be chosen enough to supply the driving circuit during the longest on-time.
- Reverse voltage rating of D1 must be above \$V_\text{High Voltage} - V_\text{CC}\$.

The input signal must be isolated from the boot-strap circuit. Some possible isolaters are:

### Optocoupler

Optocoupler is the most basic method for isolation. They are very cheap compared to other methods. The cheap ones have propagation delay times down to 3\$\mu\$s. The ones with less than 1\$\mu\$s propagation delay are as expensive as isolated gate drivers though.

### Pulse Transformer

Pulse transformer is a spacial type of transformer for transferring rectangular pulses. They have less number of turns in order to avoid parasitic capacitance and inductance and larger cores for compensating loss of inductance due to reduced number of turns. They are much faster than optocouplers. Delay times are less than 100ns in general. The image above is for illustration only. In practice, the current they can provide is not enough for driving a MOSFET fast; so they need additional circuitry in practice.

### Isolated Gate Driver

Isolated gate driving is a relatively new technology. All the complexity of gate driving is encapsulated in one single chip. They are as fast as pulse transformers, yet they can provide a few amperes of peak gate current. Some products also contain on-chip isolated DC-DC converters, so they don't even need boot-strapping. However, all these super features come with a cost.

## Best Answer

Here's how I would work out the input impedance.

At the frequencies of interest, consider C2 to be a wire.

Note then, that the output voltage appears at the bottom of R3 whilst the input voltage appears at the top.

Let the voltage gain of this circuit be \$A_{CC} < 1\$.

Then the voltage across R3 is \$v_{in} - A_{CC}\ v_{in} = v_{in}(1 - A_{CC})\$

The current through R3 is then \$\dfrac{v_{in}(1 - A_{CC})}{R_3} \$

Thus, to the input voltage source, R3 "looks" bigger by factor of \$\dfrac{1}{1 - A_{CC}} \$

Looking into the base of Q1, the impedance is approximately \$(1 + \beta)\ (R_4||R_2||R_1 + r_e) \$ where \$r_e = \frac{V_T}{I_E} \$.

Then, the input impedance is:

\$r_{in} = \dfrac{R_3}{1 - A_{CC}} || \left[(1 + \beta)\ (R_4||R_2||R_1 + r_e) \right] \$

Since the left hand term in the parallel combination is typically far larger than the right hand term, the input impedance is dominated by the right hand term, i.e.,

\$r_{in} \approx (1 + \beta)\ (R_4||R_2||R_1 + r_e)\$

For example, with \$V_T = 25mV\$ and \$I_E = 1mA\$, \$r_e = 25 \Omega \$ thus, with \$R_4||R_2||R_1 = 833 \Omega \$:

\$r_{in} \approx (1 + \beta)\ 858 \Omega \$