I am currently attempting to design an inverter in Microwind layout software that has equal rise and fall times. Rise time is defined as the time for the circuit's output to go from 10 percent to 90 percent of its full value, and fall time as 90 percent to 10 percent of its full value.
My understanding is that, since hole mobility is not as fast as electron mobility, the PMOS needs to be sized such that its width is anywhere from two to three times as great as that of the NMOS. However, it seems that I cannot get a complete match on rise and fall times.
My workflow is such that I design the inverter in Microwind, and export it as a PSPICE netlist format –using Level 3 models for the NMOS and PMOS– that I then simulate with LTspice to investigate the rise and fall times. I have done so with three cases: P-width is equal to N-width, P-width is 2.5 times N-width, and P-width is 3.0 times N-width.
I can observe the difference between rise and fall times drop from 2.277ps to 1.177ps to 1.073ps as the ratio increases from 1 to 2.5 to 3.0, respectively. However, I don't know if this is "good enough" or not. For lab purposes, my professor has indicated that it is sufficient to simply show the improvement, but I'm bothered by the difference.
Is this simply an artifact of my simulation caused by some aspect of the MOSFET models? Is this indicative of a problem with my design in layout? I've attached a netlist for the 3.0 simulation. The only parameters that seem to change from ratio to ratio are the widths of the PMOS (the "W=" parameter on the "MP1" element) and the capacitors that Microwind is adding to the netlist. I suspect this might be where I'm going wrong. If these capacitances are crunched from the physical lengths of, say, the Vdd and Gnd lines, then perhaps the additional capacitance from those lengths is sufficient to sway my rise and fall times a little bit (My Vdd and Gnd lines are not perfectly identical across layouts).
My apologies if this question has been answered, but numerous different queries to the search engine for the site didn't seem to bring up any entries that address the rise and fall time issue as investigated in simulation (Equal rise time and fall time in CMOS circuits ; this entry only seems to address the "whys" of equal rise and fall times being desirable).
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* IC Technology: CMOS 90nm - 6 Metal
*
VDD 1 0 DC 1.00
VA 6 0 PULSE(0.00 1.00 0.48N 0.03N 0.03N 0.48N 1.00N)
*
* List of nodes
* "Z" corresponds to n°3
* "A" corresponds to n°6
*
* MOS devices
MN1 0 6 3 0 N1 W= 0.80U L= 0.10U
MP1 1 6 3 1 P1 W= 2.40U L= 0.10U
*
C2 1 0 0.975fF
C3 3 0 1.160fF
C4 1 0 1.233fF
C6 6 0 0.033fF
*
* n-MOS Model 3 :
* low leakage
.MODEL N1 NMOS LEVEL=3 VTO=0.35 UO=500.000 TOX= 1.8E-9
+LD =0.008U THETA=0.300 GAMMA=0.400
+PHI=0.150 KAPPA=0.200 VMAX=130.00K
+CGSO=100.0p CGDO=100.0p
+CGBO= 60.0p CJSW=240.0p
*
* p-MOS Model 3:
* low leakage
.MODEL P1 PMOS LEVEL=3 VTO=-0.35 UO=200.000 TOX= 1.8E-9
+LD =0.008U THETA=0.300 GAMMA=0.400
+PHI=0.150 KAPPA=0.150 VMAX=100.00K
+CGSO=100.0p CGDO=100.0p
+CGBO= 60.0p CJSW=240.0p
*
* Transient analysis
*
.TEMP 27.0
.TRAN 0.01N 2.00N
* (Pspice)
.PROBE
.END
Best Answer
Model level 3 definition: "Semi-empirical" - a more qualitative model that uses observed operation to define its equations. This dates from 1980 ... Any sort of decent result (i.e. within 10% of reality) would need to use level 5 models (AKA BSIM3). I'd recommend using BSIM 3V3 which is model level 49 in Star-HSPice parlance.
As long as you going to be using out of date models then you should heed your prof and only look at the trends. I suspect that there probably is a reason he said that.
You're dealing with curve fitted results.
Additionally, unless you have parasitic extraction enabled the rail capacitances as you noted are almost certainly not being extracted. The CJSW means Capacitance, Junction Side Wall and is a computed values based upon the width and S/D sizes (as one example). There are excellent SPICE guides that tell you what all the parameters are, I suggest you find and read them.