By the problem description, the amplifier is to source a 35mA sinusoidal current through the load.
Note that during the positive half of the cycle, the output current is from left to right through the capacitor but, during the negative half, the current is from right to left.
Note also that the BJT current is (assuming the transistor is active) always out of the emitter.
Thus, during the negative half cycle, the current through the emitter resistor is the sum of the load current and BJT emitter current.
If follows that the current 'down' through the emitter resistor at the negative peak is at least \$35ma\$. This would be the case if the BJT were just 'turning off' at the negative peak.
Since it is already given that the emitter voltage should be \$7.22V\$ at the negative peak, and we know the resistor current is at least \$35mA\$ then, Ohm's Law gives
$$R_E \le \frac{7.22V}{35mA}$$
In other words, we have established an upper bound on the value of \$R_E\$.
We want maximum voltage swing, so we say the emitter DC voltage is
approximately 7.5V, half of our positive rail...
For sinusoidal operation and assuming the capacitor voltage is constant (the capacitor is an AC short circuit) and equal to the DC emitter voltage \$V_E\$, we have:
$$v_{O+} = V_+ - V_E $$
$$v_{O-} = -V_E \frac{R_L}{R_E + R_L} $$
Typically, one wants these to be equal in magnitude, i.e., we want the output voltage swing to be symmetric.
Setting \$|v_{O+}| = |v_{O-}|\$ yields the following condition for symmetric load voltage swing:
$$V_E = V_+ \frac{R_E + R_L}{R_E + 2R_L} $$
Of course, you are allowed to make Rc=Re. However, the question remains if this make much sense! Hence, I think the first rule you have mentioned (Vc=Vcc*2/3 and Ve=Vcc/3) is a good trade-off between allowable swing and good stabilization of the operational point. As you probably know, the resistor Re provides negative feedback for DC and stabilizes the bias point.
Regarding your example (Vcc=12V). In this case the possible (theoretical) swing is 12-8=+4V and 4-8=-4V with Vce=4V.
Of course, the resistor Re provides also signal feedback, thereby reducing the gain to a value of app. Rc/Re. For larger gain you can bypass the resistor Re with a suitable capacitor.
Best Answer
jm567 - perhaps you have forgotten that the collector current depends on the base-emitter voltage. It is the well-known exponential relation Ic=f(Vbe). When the base voltage Vb remains fixed and the emitter voltage Ve increases, the voltage difference Vb-Ve=Vbe decreases - and with it the collector current. As a consequence, the collector voltage increases.
Comment 1 (Edit): I like to take the chance for comparing the two possible explanations for controlling the collector current in a common-base stage:
(1) An externally applied RISING signal voltage at the emitter node will REDUCE the voltage Vbe and, therefore, REDUCE the emitter current according to Ie=f[exp(Vbe/Vt)]. Because of Ie=Ib+Ic both currents, Ib and Ic, will also DECREASE by the same exponenetial expression. This is because there is a nearly constant relationship between Ic and Ib (beta).
(2) An externally applied RISING signal voltage will cause a corresponding (small) current change delta(ib) from the emitter to the base (thereby REDUCING the postive DC base bias current +Ib in opposite direction) - however, this small base current change delta(ib) is part of a larger current change delta(ie) because of delta(ie)=delta(ib)+delta(ic).
I think, it is obvious that delta(ib) is NOT the physical reason for delta(ic). All the currents change at the same time due to Vbe change in the same direction.
Comment 2: I must admit that I really cannot understand some parts of the discussion about the "common base amplifier confusion" (title). The questioner could not see how the collector current will decrease when the voltage at the emitter node of the shown circuit increases (due to an input signal).
Is there any doubt that the transistor will allow an emitter current Ie when the device is "opened" with a voltage Vbe=0.7V and that this current Ie is split into Ie=Ib+Ic? Is there any doubt that this current will be smaller for Vbe=0.65 V ? So - what is the problem? The voltage Vbe=Vb-Ve will be reduced when the emitter voltage Ve is slightly increased due to the input voltage Vi at the emitter node. As a consequence, all three currents (Ie,Ib,Ic) will - according to Ie=Ib+Ic - decrease. Thats all!
I cannot understand why - according to a written comment below - this view should be "misleading"?