I am working on a project which uses a PIC24FJ64GA002 mcu.
I am working on a bit-banged serial communication function that will use one wire to send data and then switch to receive mode to receive data on the same pin. A separate pin will be used for clocking which will always be controlled by a different board (always an input). I am wondering is there a way to configure the pin for open-collector operation that that it can be used as an input and and output or do I have to change the pin configuration every time i go from reading to writing?
Electronic – Configure a PIC pin for Input and Output
inputoutputpicport
Related Solutions
You don't need dual-port RAM or even a serial RAM with two interfaces; For SPI it's a little trickier, but I2C allows multiple masters "out of the box." Either way, your software will have to monitor the bus conditions to see if it lost the bus and if so, wait for another opportunity.
For SPI, the MOSI, CS and CLK lines must be tri-stated (or open-collector) with pull-up resistors to keep the lines from floating. You will also need some kind of bus arbitration. This can be as simple as a single GPIO between the two masters so that the one with higher priority signals the lower-priority master that the bus is unavailable, but a more elegant solution would be a single open-collector line between the masters. When the bus is idle, neither master is yanking the line down so it floats high with a pull-up. The logic is that if the line is high, the bus is available. The master that wants to use the memory would look at the "bus available" line and if it's high, drive the line low and wait a few ms to make sure the other master didn't grab the bus at the same time. If the RAM SPI CS line is still inactive, it can be safe to assume that the bus is yours. Do the transfer, tri-state your MOSI/CLK lines and let go of the "bus active" signal.
The "wait a few ms after yanking the bus request line low" is necessary since it is possible for both masters to grab the line at the same time.
If you are only ever using one shared device and that device does not require multiple transfers, you could use its CS line as the "bus available" signal, but this isn't quite as robust.
The PassMark web site, the company whose software is being used, provides the loopback connection pin-outs for the relevant types of connectors, including 9 pin DE-9 Serial, 25 pin DB-25 Serial, and 25-pin DB-25 Parallel.
The pin-out that failed was for DB-25 Serial connectors. The DB-25 parallel port loopback connection is provided:
- Data 0 and Error status (Pin 2 & 15)
- Data 1 and Select status (3 & 13)
- Data 2 and Paper out status (4 & 12)
- Data 3 and Acknowledge status (5 & 10)
- Data 4 and Busy status (6 & 11)
They also provide a diagram, of the male DB-25 connector as seen from its rear:
Also relevant, PassMark recommends that the parallel port be set to ECP or EPP mode, and not SPP mode, for loopback testing to work.
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Best Answer
Change the pin configuration every time. It's the TRIS register that controls if it's an input (1) or output (0). And, when you change direction, you have to wait a moment (check the datasheet) like a cycle or two before you use that pin. a couple Nop(); will do fine.
And, make sure you write to the LAT register, and read from the R register.
e.g. for port D, pin 0.