According to David Harris's presentation for eve224a course: (slides 6-11 and 47)
Delay d = f+p = g*h+p
Where d is process-independent delay, f is effort delay (stage effect), p is parasitic delay, g is logical effort, h is electrical effort (fanout; h = C_out/C_in)
In the Wikipedia article "Logical Effort" there are some examples too:
Delay in an inverter. By definition, the logical effort g of an inverter is 1
Delay in NAND and NOR gates. The logical effort of a two-input NAND gate is calculated to be g = 4/3
For NOT gate with FO1 (driving the same NOT gate):
g=1; h=1; p=1; so d = 1*1 + 1 = 2
For NOT gate with FO4 (the FO4 metric itself):
g=1; h=4 (Cout is 4 times more than Cin); p=1 so d = 1*4+1 =5 (the same result is at page 20 of books "Logical Effort: Designing Fast CMOS Circuits", draft from 1998)
1 FO4 delay is equal to 5 process-independent units (defined by harris, slide 6)
For NAND gate with two inputs (p=2) which drives the same:
g=4/3; h=1; p=2; d= 4/3 * 1 + 2 = 10/3 = 3,3 (a 1.5 times slower than NOT with FO1, but faster than NOT FO4)
For NAND gate asked by me - 2 inputs which drives 3 same NANDs:
g=4/3; h=3; p=2; d= (some magic inside) 4/3 * 3 + 2 = 6
So
Delay of 1 FO4 gate is equal to 5/6 delay of NAND (2-in, 3 FO).
The last problem is to convert chain delay of 18 NANDs to chain delay of FO4. (slide 41 of harris)
Hmm.. seems I need only to multiply 18 NANDs delay with 6/5... 21,6 FO4.
Thanks!
No, the circuit structures to produce gates in TTL and CMOS are very different.
It's actually a very complex topic, because at this level, you can't just treat transistors (BJTs or FETs) as simple "switches". It becomes an analog circuit design problem in which many issues need to be considered: how static and dynamic currents flow, where charges are stored on the various internal "nodes", connectivity among gates (fan-in and fan-out), etc.
Also, different types of transistor technology have different ways in which they can be applied. "True" TTL (74xx, 74Lxx, 74Hxx, 74Sxx) uses a single multi-emitter transistor to create a basic NAND structure with an arbitrary number of inputs; the rest of the circuitry is basically buffers so that the gate can drive the next gate(s) downstream.
LSTTL is really an advanced form of DTL (diode-transistor logic), in which the basic structure is an AND gate; again, the transistors are mainly for buffering.
In CMOS, the basic structure is a 2-transistor inverter. To create other logic functions, additional transistors are added in series/parallel with the original pullup/pulldown transistors of the inverter. Ideally, there is no static current draw at all, just the dynamic current of charging and discharging gate capacitances.
PMOS and NMOS were never offered as standardized gates in SSI/MSI packages, but these technologies were widely used in custom IC design for quite a while. The basic gate structure is basically half a CMOS gate, but with a passive pullup (a transistor used as a current source) as a load. All of the early microprocessor chips were built with these technologies.
Any technology based on MOS transistors has very high input impedances, which means that charge storage is a viable way of remembering data values, at least for short time periods. This can save a lot of transistors, and is why most early microprocessors had minimum as well as maximum clock frequencies. This technique can't be used with BJT technology.
Best Answer
Like others have already said (I'll just be a little more elaborate), unused CMOS input pins must never be unconnected, because they tend to float towards the dangerous region which is in the middle between VDD and GND. The input pin invariably is connected to another complementary MOS pair's gates, and the process parameters are often optimized for performance so that both the high side and the low side will start conducting a little earlier than in the exact middle point. So in this "middle gray area", both the high side and the low side FETs will conduct some electricity, which results in current consumption, or in some cases, even oscillation if there's a positive feedback path to be found somewhere.
The easiest case and electrically the most stable case is to connect all unused CMOS inputs to ground. But in microcontrollers this can be a little dangerous, because software may make use pins as inputs or outputs. A software update might then make an output from a pin which has previously been unused. In this case, the safest option is to use separate pull-down resistors for each pin. If that is too costly due to the number of resistors and PCB space needed, you can also connect a group of adjacent pins together and pull them low with a single pull-down resistor. In that case, the extra current consumption caused by the surprise software change is usually not that big a problem.
In your specific case of using a hex inverter, there is yet another possibility, which is often used. You can connect the unused inverter inputs and outputs together with some inverter, which is used in the system: connect several inverters in parallel. This is often done to increase the drive capability and thus speed of the inverter, especially when driving large MOSFET gate loads.