Logic gates like AND, OR, NOT etc. often come packed as arrays in ICs.
Sometimes not all gates are used in a project. I would like to know how the remaining unused gates should be connected to achieve minimal influence on the system (energy consumption, interference) based on which technology (CMOS, TTL,…) is used.
My application uses a CMOS based hex inverter (CD4069) and the documentation doesnt provide this information.
Note: This is not about several inputs to a single logic gate. In this case connection of the unused pins would be the consequence of keeping the gate functional.