Electronic – Constellation diagram of FSK

Let's see if I can guess how this is meant to be interpreted:

1. We have two basis functions, giving us a two-dimensional space in which to align symbols.

2. For successful decoding, the basis functions need to be at least linearly independent, and ideally, they should be orthogonal.

3. Testing for orthogonality, we multiply and integrate:

   \$\int\Phi_1(t)\Phi_2(t)dt = 0\$

4. Good thing that worked, otherwise we would have had to prove \$\nexists x | \Phi_1(t) = x\Phi_2(t)\$.

   For a two-basis system, that is somewhat sane, but with more basis functions, this starts to get really cumbersome. Fortunately, non-orthogonal systems are not that relevant in practice.

5. The amplitude is written in a manner that I find to be completely non-intuitive. Someone more enlightened than me could possibly comment on how that is useful beyond hinting at #7 below.

6. Constructing the time representation for each symbol is straightforward -- you multiply the symbol's constellation position with the basis function, and add these up (i.e. all you do here is a basis transformation of a vector):

   \$S_1(t) = (2V\sqrt{T_b})\Phi_1(t) + (-2V\sqrt{T_b})\Phi2(t)\$

7. This system is equivalent to a Fourier transformation with two points. \$\Phi_1(t)\$ is the DC part, \$\Phi_2(t)\$ is the base frequency. Decoding this schema works likewise, by multiplying the basis function again, and correcting the linear amplification resulting from the integration (probably that's why the \$1/\sqrt{T_b}\$ is there).

   The difference with the square waves is that you need to reconstruct the timing, which I assume is pretty much a given in that hypothetical scenario. If you don't have the timing information, the multiplication and integration become a full convolution, and you have to find the middle of the symbol.

8. The decision boundary would most likely be placed so that for each constellation point, the nearest valid symbol is selected. You have two valid symbols, so just draw a line in the middle between them.

Some thoughts but certainly not a full design: -

The modulator is a lot simpler than the demodulator. For each data bit, the number of oscillation cycles is as follows: -

• Bit = high, number of clock cycles is 4.516 MHz divided by 564.48 k = 8.0 cycles
• Bit = low, number of clock cycles is 3.951 MHz divided by 564.48 k = 7.0 cycles

So, for the modulator, you need two clock frequencies that are chosen depending on what logical level the data bit is. The clock frequencies should be phase synchronous in that when the last clock is despatched and the bit changes, the lower clock immediately starts at a transition from low to high. This is important but not hard to achieve.

For the demodulator there is more dificulty due to the counts of cycles being very close. So I would be tempted to use a much higher-speed counter that can be used to measure the period of each received pulse. A PLL could be used - it might be possible but with only 7 or 8 clock cycles to distinguish between logical 0 or 1, it might be a bit tricky for a beginner.

Having said that, a PLL could be used to obtain the average of the two FSK frequencies - you then have a centralized reference frequency that can be used with appropriate logic circuits to decode a 0 or 1. This only works if the two frequencies produced are phase synchronous as previously described. However, the data to be sent should be scrambled so that there are no long periods where the data rests in one logical state or the other.

As for performance in the presense of noise, the lack of cycles for each bit means there could be some problems.