Electronic – Could I use a 2Ch 6bit LVDS cable on an LCD that uses 1Ch 6 bit LVDS

The 3.3V will be recognised as a high-level by TTL logic. You will need 5V to power the LCD, however.

EDIT

From the Spartan-3E User Guide:

The character LCD is power by +5V. The FPGA I/O signals are powered by 3.3V. However, the FPGA’s output levels are recognized as valid Low or High logic levels by the LCD. The LCD controller accepts 5V TTL signal levels and the 3.3V LVCMOS outputs provided by the FPGA meet the 5V TTL voltage level requirements.

The 390Ω series resistors on the data lines prevent overstressing on the FPGA and StrataFlash I/O pins when the character LCD drives a High logic value. The character LCD drives the data lines when LCD_RW is High. Most applications treat the LCD as a writeonly peripheral and never read from from the display.

The two pins are for the EDID (display identifier). Your controller may not have connections for it, or they may be on another connector.

If no connections are present, these can be left either floating or connected with a weak pull-up resistor to VEEDID. In this case the driver probably has some built in configuration that allows it to specify to the graphics card what resolution it should be.