Electronic – CPU/Processor error rate in calculations

A detailed answer is not so much a company secret, but rather the subject of several semesters at a University. Don't expect to get a complete answer here.

One of the best books on the topic is this one: http://www.amazon.com/Computer-Architecture-Fifth-Quantitative-Approach/dp/012383872X/ref=ntt_at_ep_dpt_1

There are also numerous books on digital logic design that would be good to read as well.

Your basic synchronous digital design is a sort of discrete time feedback loop.

One or more registers made of flip-flop like storage elements hold values. These flow onto buses, possibly through path selectors called multiplexers and various combinatorial logic circuits which perform a logical or arithmetic operation on the value represented by some number of signals (typically each signal being a binary digit, or bit). Over a short period of time, the result flowing through the paths and logic to circle back to the inputs of the registers stabilizes. After an interval calculated to safely allow the worst case time needed for this, another active clock edge occurs, which causes one or more of the registers to replace the current values they have been holding with the updated values being fed back to their inputs.

In the case of something like a (synchronous) a counter, the logic circuit sitting between the outputs of the registers and the inputs would add one, so each active clock edge would see the stored value increase by one.

More complicated operations such as performed by a CPU might select two source numbers from a register array from which two locations can be simultaneously accessed through two separate read ports, add them together, and write them back to somewhere in that same register array through a third writing port.