I asked a question some time ago about crossing clock domains
Design practice crossing clock domains and async signals.
One of the "rules" is to never synchronize multi-bit signal bit-by-bit, because of timing glitches between individual bits.
I have now a design, where I need to cross a multibit signal from a 27MHz domain to a 54MHz clock domain.
I have no more FIFO's left in my fpga, so is there any way to do this without using an async fifo?
Is it possible to synchronize the multibit signal, and set some timing constraint, so I at least get an error if timing is not kept?