1.- Yes, sure. You always must attend the EMC performance of your electronics design.
EMC or Signal Integrity, we are talking about the same. Although probably It's a hobbyist-project and you won't need to pass an emission or immunity EMC test in a EMC Lab but EMC is also the noise, the crosstalk or ground bounce and this could be a problem inside your project.
So, yes. For emission you can check: (only a summary)
- Raise/Fall Time in high speed signals.
- Layout of high speed. (Changes of layers, loop current...)
- Possible antennas. (Your connector and your cables could work as an antennas)
2.- It would better if you explain us more about your circuit.
I suppose there is a component that works as a switch. The out of this component we can call it "switch node". In this node the voltage is
$$V = L (di/dt) $$
; V is voltage, L the inductance of the node, i is the current, and $$di/dt$$ is the rise time (or fall time) of change.
This parameter is really important!
Maybe you can:
- Decrease the rise time. (Could it work slower?)
- Decrease the voltage (Could you use a lower voltage?)
- Decrease the inductance in your switch node.
- Include a snubber (a circuit for absorb the voltage peak).
3.- This question is the similar to 2 isn't it?
You can do relative measurements with a spectrum analyzer. Without a properly set up calibrated test range, you won't be able to make absolute measurement, but you don't really need to either.
You do need to be very careful that all the measurements you take are repeatable. When I've done this, I've taped down the receiving antenna that feeds the spectrum analyzer under the table, taped down the feed wire to it, marked with tape exactly where on the table the unit under test goes, and taped down any cables that go to the unit that are necessary to test it.
Once you have a repeatable setup, take a bunch of readings as a baseline, and then write down or otherwise carefully record the results. Modern units have ways of getting data out and onto your PC where you can save it, but just a old fashioned picture of the analyzer screen can be good enough too.
Once you have a baseline, you can make modifications and see the relative results. Don't expect the changes to have exactly the same relative effect later on the calibrated test range, but if you are 3 dB over at a particular frequency and you knock down that peak by 15 dB, you'll be OK. Your measurements will be near field, but in practise that doesn't matter much. Figure at least 3 dB is slop, so you want to bring any offending peaks down by at least 3 dB more than the original test says they need to be. 6 dB is a lot better. Chances are you can knock most of the peaks down by 15 dB or more with just a few basic modifications.
The best way to avoid EMI problems is to design for that in the first place. The single most important thing you can do is to have a good grounding strategy. A pervasive ground plane is good, but not if every little connection punches down to the ground plane. Then you have a center-fed patch antenna. Keep local high frequency loop currents local and off the main ground plane.
Another obvious thing to do is to put small capacitors to the main ground plane on all signals that go off board, right where they leave the board. Sometimes this is not possible due to the nature of the signals or the isolation required, but even a few 10s of pF can make a big difference. Many signals can tolerate that since most cables will expose them to more than that anyway.
Radiated noise tends to be common mode, so baluns on differential signals can help a lot. Most ethernet transformers, for example, come with baluns on the network-side pairs for that reason. In that case you don't want to use caps to ground due to the isolation requirements, but the baluns built into the transformers usually do a good enough job anyway.
To test whether emissions are escaping as common mode signals on a cable, clamp a ferrite around the cable and see if that reduces the peak. If it does, you have a common mode emission problem on that cable.
Whole books could be written about this, so there is too much to get into here. Go find someone that has been thru this before to help you this time. Be prepared that the answer may mean a re-layouot with RF emissions considered. You can only bandaid a bad layout so far.
Best Answer
You should change your terminology to 'oscillator' instead of crystal. Oscillators are the type of component with an OE pin such as you have and require quite different layout requirements than those required by a crystal. We should also see the schematic of the oscillator connections and we should know the oscillator frequency.
In general your circuit and wiring for the oscillator should follow the sequence below:
a) Make sure that the oscillator circuitry is matched with a full pour GND plane under it.
b) Make sure to bypass the oscillator Vcc and GND connections in a way that there is copper without vias between the both sides of the bypass capacitor and the oscillator pins.
c) Keep the copper length between the bypass capacitor and the oscillator pins as short as possible.
d) Place a small value resistor in series with the oscillator output. The copper distance from the oscillator output to the resistor should be as short as possible. Resistor value can be determined from simulations done during signal integrity analysis or can be selected by value swapping on your prototype PCB and observing signal quality on a good quality oscilloscope.
e) Route the clock signal from the resistor to the nearest destination load and minimize the number of vias on the way. Best is no vias.
f) Continue the clock route from the first load as series layout. (Do not take the clock signal and route it as a branched Y to the two loads). The continued series connection is best if it simply passes through the pad of the first load. If a stub to the first load is required then keep it as absolutely as short as possible.
g) Route the series clock signal to the second load where it will terminate at the pad. Minimize the number of vias in the path. Best is no vias.
h) It can be an advantage to route the critical clock signal first in the layout so you can achieve the above goals. Then fit the remaining traces around this initial layout. Do note that the clock signal can couple to adjacent parallel signal routes in the same layer or in adjacent layers. You should check carefully that any adjacent signal routes are non-sensitive to some coupling, are not very long traces the go all over the board and are not signal lines that go off plane or out to I/O connectors. If parallel routes cannot be avoided then it may be necessary to impose minimum spacing design rules to help minimize the amount of coupling.