Electronic – Data bus between uC and SRAM: what happens when both are writing concurrently

busmicrocontrollersram

My understanding of interfacing a standard SRAM chip is the following: When the host wants to write, the OutputEnable# is driven high to bring the SRAM data bus to High-Z and the host is driving the bus. When reading, OutputEnable# is low and the SRAM is driving the bus.

What happens if I accidentially enable the output of the SRAM while driving the outputs on the host side at the same time? Will there be physical damage?

Best Answer

Yes, there may be physical damage. The longer the situation persists, the more the chance for damage. In case this is a problem you foresee happening often in your setup, you should probably work out a better scheme, or at the very least include a series resistor in each of the data lines. The resistor should be chosen such that in the worst case (both sides driving to opposite logic), the current through the resistor should be less than the current drive capability of the IC with the lower current drive capability. Note that in doing so, you will most definitely sacrifice in the speed the data bus is capable of operating at without the series resistance.