Let's take a single 8-bit 200MHz DDR chip. All datasheets state that bandwidth is "up to" 400MB/s.
Because it's dual, data is read/written on both edges so yes, theoretical, it's 400MB/s.
But you need 4 or 5 cycles to do a 4-byte burst read operation which 2 cycles are used to "really" read data (4 edges).
400MB/s would imply 2 cycles for each read.
If you optimize like crazy with CAS-latency=2, I don't see how you can do fewer than 4 cycles.
The real sustained read speed of a single DDR chip is 400MB/s * 2/4 = 200MB/s. And I even don't mention the refresh operations…
Am I misunderstanding the specifications?
Best Answer
A 200 MHz DDR chip has a maximum bus bandwidth of 400MT/s. It does not mean it can transfer data constantly at that speed. The commands what to read are also sent on this bus, and the requested data is available after the latency period. When the data is available, a block of data can be transferred at full 400MT/s rate.
Usually the maximum memory speed is stated but the chip can be used at lower bus speed. In this case the latency has less clock cycles and the data transfer is just slower.
Edit: So what was missing from my answer was that the burst read commands can be arranged so that the data bursts can be transmitted consecutively.