Electronic – Dead-time in Full Bridge Inverter (LTSpice Simulation)

full-bridgeinverterltspicepower electronicssimulation

I am trying to generate a dead time between two switching legs in the conventional full bridge inverter. However, by simply including the delay block for one pair of switches – just shifts the signal with the same duty ratio, resulting in cross conduction for the following sub interval. The duty ratio is generated by comparing the saw tooth signal against the reference sine wave.
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Any suggestions how to generate pulses without cross over? Thanks in advance.

UPDATE

I implemented dead time with the proposed RC and Differential Schmitt block. However, decided to stick with the DS. I have been trying to understand this very hard, but still no idea if the dead time is actually doing anything or not? From the graph below (top right) you can see how both pairs of switches are cross conducting even though drive signal clearly has a specified dead time (below). I also varied some of the SW parameters, but didn't see much of a difference apart from more graduate, softer transitions. Any idea if I should dwell on this further or can I just assume that they are "successfully" driven with a dead time?enter image description here

Best Answer

Duty cycle shortener (winny's suggested name): -

enter image description here

The lower waveform in the picture above can be used for top-left and bottom-right switches. An inverted version of the middle waveform (use a NAND gate instead) can be used to activate top-right and bottom-left switches.

  • Choose logic gates that have schmitt trigger inputs.
  • Choose RC to give appropriate time delay in line with schmitt trigger input levels.