I'm trying to design a de-bouncer circuit , which is widely used in digital design . The module that I'm trying to implement is as shown below :-
I've written the following Verilog Module :-
`timescale 1ns / 1ps
module debounce_ckt(
input button,
input clk,
output reg result
);
/************************************* Internal Variables **********************************/
reg Q1;
reg Q2;
wire EN1 = 1'b1;
wire EN2 = 1'b1;
wire xor_out;
/****************************** Debounce ckt Implementation code ****************************************/
DFF FF1 (button,clk,EN1,Q1);
DFF FF2 (Q1,clk,EN2,Q2);
xor g1 (xor_out,Q1,Q2);
counter C1 (clk,xor_out,~Cout,Cout);
DFF FF3 (Q2,clk,Cout,result);
endmodule
/***************************************** N-bit counter *************************************/
module counter (clk, SCLR,EN,Cout);
input clk;
input SCLR; // Clear of counter //
input EN ; // Active 'HIGH' Enable //
output reg [N-1:0] Cout; // Counter Output //
// Time period of debounce ckt = T = (2^N + 2)/ f //
// 'f' is the input clock frequency //
// 'N' is the mod value of counter //
parameter N = 16;
always@(posedge clk)
if(SCLR) Cout <= 0;
else if (EN)
begin
if (Cout == N-1)
Cout <= 0;
else
Cout <= Cout + 1;
end
endmodule
/************************************* D Flip Flop Module (with Enable)**************************/
module DFF(input D,input clk,input EN ,output reg Q);
always @(posedge clk or EN)
begin
if(EN)
begin
Q <= D;
end
end
endmodule
Testbench is as follows :-
`timescale 1ns / 1ps
module tb;
// Inputs
reg button;
reg clk;
// Outputs
wire result;
// Instantiate the Unit Under Test (UUT)
debounce_ckt uut (
.button(button),
.clk(clk),
.result(result)
);
initial begin
clk = 1'b0;
end
always #5 clk = ~ clk;
initial begin
#12 button = 0;#10 button = 0 ; #10 button = 1 ; #10 button = 0 ;
#12 button = 1;#10 button = 1 ; #10 button = 0 ; #10 button = 1 ;
#12 button = 1;#10 button = 0 ; #10 button = 0 ; #10 button = 1 ;
#12 button = 0;#10 button = 1 ; #10 button = 1 ; #10 button = 0 ;
#10 $finish;
end
endmodule
The output 'result' is going to 'X' don't care state, when I'm trying to simulate the files.
Can anyone point out where the issue lies and what corrections are to be made. I'm not expecting a whole working code in the answer. I'd just want to know the error in my code which is causing this.
Best Answer
Debouncer
This debouncer assumes that its input is synchronised to the clock.
The output will only change state when the input has been in the opposite state for N clock cycles, i.e. a form of hysteresis to produce a kind of low pass filter.
The counter only counts when the input and output differ, thus reducing switching losses when the input equals the output.
Synchroniser
All asynchronous inputs, such as buttons, need to be synchronised to the clock something like this:
The output of the synchroniser should be connected to the input of the debouncer.
Test Bench
I increased the button timings and reduced
MAX_COUNT
to see the debouncing effect.Simulation
This shows the debounced button signal with edge detect (both, rise and fall).
It takes 3 clock cycles to synchronise the input and 4 clock cycles to debounce it.