Electronic – Declaring vector variable in the Verilog not starting with the MSB(e.g,. reg var[0][20])

verilog

I am familiar to the syntax described in here

net_type [msb:lsb] list_of_net_identifiers;

reg [msb:lsb] list_of_register_identifiers;

For example, to declare the 32bits memory address, I could use the syntax like

reg [31:0] address;

Also to declare the memory comprised of the 16 elements which consist of 32 bits each,

reg [31:0] mem [15:0];

However, I could frequently face the syntax like below to declare multidimensional arrays.

reg [31:0] mem [0:15]

I've googled it and found one related article in here.
It seems that whether the larger number comes first or not, the first number before the colon (:) is the MSB and the LSB follows. It seems like the difference comes from the preference of coding.

However, I think mixing [31:0] and [0:15] style is little bit count-intuitive and confusing even though it depends on the preference. I could see a lot of mixing especially in the declaration of multi-dimensional arrays. Why is it allowed to be used? Is there any advantage that I couldn't notice?

Best Answer

In Verilog, the numeric index ordering of a memory is only a matter of preference except when loading the memory from a text file. The first line in the file represents the left index, and like most other languages, starts at 0, so [0:15] is the more common way to declare a memory range. Otherwise there is no advantage one way or the other in how you declare a memory range since you canny only reference one memory element at a time.

The same can be said about a vector if you never plan to access individual bits of the vector. But once you do, how you address each bit becomes significant in position of an integral value.

In SystemVerilog, the ordering of both the vector width and memory dimensions becomes significant because you can stream memories as a whole and well as selects parts just like you do a vector.

Related Solutions

Electronic – the difference between an array and a bus in Verilog

A bus enables you to define values that are wider than one bit. If you want to store or transmit (in parallel) a value between 0 and 15, you need a 4-bit bus. An array lets you store multiple values under a single name.

The difference between "[7:0] data" and "data[7:0]" is that the first is a single 8-bit-wide value while the second is eight single-bit values.

It's totally normal and useful to create an array of busses. They're sometimes called memories, because you can use them to model ROM or RAM. Your synthesis software can usually recognize when you've defined something that looks like ROM or RAM (for example, reg [7:0] data[1023:0] is basically 1K by 8-bit RAM) and synthesize it as actual physical ROM or RAM on the chip.

To understand which construct to use, just ask yourself what you have. Do you have a single multi-bit value? That's a bus. Do you have a bunch of single-bit values that you want to reference using a single name? Then use an array. Do you have a bunch of multi-bit values? Then use a memory.

Electronic – Is it right to initialize a reg in verilog and apply condition with initial value of reg in Verilog

Initialising the registers at declaration is perfectly synthesisable. It tells the compiler what the power-on value of the register should be. Generally the initial value for the registers is always 0 anyway, and if you choose to have them set to 1, it will basically use bubble pushing optimisations to invert the register value and still use 0 as the initial value (but as far as your logic is concerned it would effectively be 1).

However, for anything other than a data bus (qualified by some valid signal), this is not recommended. Why? because of what happens if you have a reset signal somewhere else in your logic. If half of your logic is reset at some point and you have a control signal that only has a power-on initial value and not a reset, then your two cores go out of sync - one is in in a nice known reset state, the other is in whatever unknown state it was when the reset occurred. For qualified data signals, a don't care/unknown value doesn't matter as long as the valid-like signal is reset to a known state of invalid.

The better practice is to use a reset signal for all control and valid signals to have a reset value, either synchronous or asynchronous. This eliminates the need for an initial power-on value requirement (you can still add it, but it's no longer required). The power-on value will be determined by the synthesizer based on the requested reset value.

always @ (<edge> clock or posedge reset) begin
    if (reset) begin
        //Reset value goes in here, this value also determines power-on value.
    end else ...

    end
end

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